公开(公告)号：US12224217B2

公开(公告)日：2025-02-11

申请号：US16811161

申请日：2020-03-06

Applicant: Cree, Inc.

Inventor： Richard Wilson ,  Haedong Jang ,  Simon Ward ,  Madhu Chidurala

IPC: H01L23/043 ,  H01L21/48 ,  H01L23/495

Abstract: A radio frequency (RF) package includes a support having a semiconductor die attach region; a frame that includes an electrically insulative member having a lower side attached to the support and an upper side opposite the support; the frame includes an opening at least partially registered with said semiconductor die attach region; and the frame includes an upper metallization at the upper side of the electrically insulative member and a lower metallization The frame includes first electrically conductive edge connection connecting the first metallization to the first lower metallization.

公开(公告)号：US12159817B2

公开(公告)日：2024-12-03

申请号：US17371410

申请日：2021-07-09

Applicant: Cree, Inc.

Inventor： Sung Chul Joo ,  Ulf Hakan Andre

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/66 ,  H05K1/18 ,  H05K3/34

Abstract: A semiconductor device comprises a lead, a board, and an electrically conductive layer on the board. The lead comprises a longitudinal axis and is soldered to the electrically conductive layer. The semiconductor device further comprises a first solder dam edge and a second solder dam edge, each positioned on the lead not more than 10 mils apart from each other along the longitudinal axis.

公开(公告)号：US11862719B2

公开(公告)日：2024-01-02

申请号：US17123727

申请日：2020-12-16

Applicant: CREE, INC.

Inventor： Saptharishi Sriram ,  Thomas Smith ,  Alexander Suvorov ,  Christer Hallin

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40 ,  H01L29/10

CPC classification number: H01L29/7786 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41725 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/1066 ,  H01L29/41766

Abstract: An apparatus includes a substrate. The apparatus further includes a group III-nitride buffer layer on the substrate; a group III-nitride barrier layer on the group III-nitride buffer layer, the group III-nitride barrier layer including a higher bandgap than a bandgap of the group III-nitride buffer layer. The apparatus further includes a source electrically coupled to the group III-nitride barrier layer; a gate electrically coupled to the group III-nitride barrier layer; a drain electrically coupled to the group III-nitride barrier layer; and a p-region being at least one of the following: in the substrate or on the substrate below said group III-nitride barrier layer.

公开(公告)号：US20230010770A1

公开(公告)日：2023-01-12

申请号：US17371410

申请日：2021-07-09

Applicant: Cree, Inc.

Inventor： Sung Chul Joo ,  Ulf Hakan Andre

IPC: H01L23/495 ,  H01L23/66 ,  H01L23/31

Abstract: A semiconductor device comprises a lead, a board, and an electrically conductive layer on the board. The lead comprises a longitudinal axis and is soldered to the electrically conductive layer. The semiconductor device further comprises a first solder dam edge and a second solder dam edge, each positioned on the lead not more than 10 mils apart from each other along the longitudinal axis.

公开(公告)号：US20220399318A1

公开(公告)日：2022-12-15

申请号：US17342925

申请日：2021-06-09

Applicant: CREE, INC

Inventor： Eng Wah WOO ,  Samantha CHEANG ,  Kok Meng KAM ,  Marvin MABELL ,  Haedong JANG ,  Alexander KOMPOSCH

IPC: H01L25/16 ,  H01L23/00 ,  H01L23/047 ,  H01L23/66 ,  H01L21/48

Abstract: A transistor package that includes a metal submount; a transistor die mounted on said metal submount; a surface mount IPD component that includes a dielectric substrate; and the dielectric substrate mounted on said metal submount. Additionally, the dielectric substrate includes one of the following: an irregular shape, a non-square shape, and a nonrectangular shape.

公开(公告)号：US20220392857A1

公开(公告)日：2022-12-08

申请号：US17340492

申请日：2021-06-07

Applicant: Cree Inc.

Inventor： David Rice ,  Jeremy Fisher

IPC: H01L23/66 ,  H03F3/195 ,  H01P3/08 ,  H01L23/00

Abstract: A packaged RF transistor amplifier includes an RF transistor amplifier die having a first terminal, a first lead, an integrated passive device that includes a first series microstrip transmission line, a first bond wire coupled between the first terminal and the first series microstrip transmission line, and a second bond wire coupled between the first series microstrip transmission line and the first lead.

公开(公告)号：US20220376104A1

公开(公告)日：2022-11-24

申请号：US17325488

申请日：2021-05-20

Applicant: Cree, Inc.

Inventor： Joshua Bisges ,  Kyle Bothe ,  Matthew King

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/10 ,  H01L29/205 ,  H01L21/263

Abstract: A transistor device includes a semiconductor structure, source and drain contacts on the semiconductor structure, a gate on the semiconductor structure between the source and drain contacts, and a surface passivation layer on the semiconductor structure between the gate and the source or drain contact. The surface passivation layer includes an opening therein that exposes a first region of the semiconductor structure for processing the first region differently than a second region of the semiconductor structure adjacent the gate. Related devices and fabrication methods are also discussed.

公开(公告)号：US20220376099A1

公开(公告)日：2022-11-24

申请号：US17325765

申请日：2021-05-20

Applicant: Cree, Inc.

Inventor： Kyle Bothe ,  Joshua Bisges

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/40 ,  H01L21/76 ,  H01L21/765 ,  H01L29/66 ,  H03F3/213 ,  H03F1/42

Abstract: A GaN-based high electron mobility transistor (HEMT) device includes a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate, a drain contact and a source contact on the barrier layer, and a gate contact on the barrier layer between the drain contact and the source contact. A sheet resistance of a drain access region and/or a source access region of the semiconductor structure is between 300 and 400 Ω/sq.

公开(公告)号：US20220367696A1

公开(公告)日：2022-11-17

申请号：US17321992

申请日：2021-05-17

Applicant: CREE, INC.

Inventor： Thomas J. SMITH, JR. ,  Saptharishi SRIRAM ,  Charles W. RICHARDS, IV

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L21/76 ,  H01L21/765 ,  H01L29/66 ,  H02H3/06 ,  H02H3/12

Abstract: An apparatus includes a substrate; a group III-Nitride barrier layer; a source electrically coupled to the group III-Nitride barrier layer; a gate on the group III-Nitride barrier layer; a drain electrically coupled to the group III-Nitride barrier layer; a p-region being arranged at or below the group III-Nitride barrier layer; and a recovery enhancement circuit configured to reduce an impact of an overload received by the gate. Additionally, at least a portion of the p-region is arranged vertically below at least one of the following: the source, the gate, an area between the gate and the drain.

公开(公告)号：US20220278212A1

公开(公告)日：2022-09-01

申请号：US17188329

申请日：2021-03-01

Applicant: Cree, Inc.

Inventor： Sei-Hyung Ryu ,  Thomas E. Harrington, III

IPC: H01L29/423 ,  H01L29/40

Abstract: Power semiconductor devices include a semiconductor layer structure comprising an active area with a plurality of unit cell transistors and an inactive gate pad area, a gate resistor layer on an upper side of the semiconductor layer structure, an inner contact that is directly on the upper side of the gate resistor layer, and an outer contact that is directly on the upper side of the gate resistor layer. The outer contact encloses the inner contact within the inactive gate pad area of the semiconductor device.