公开(公告)号：US09117654B2

公开(公告)日：2015-08-25

申请号：US13470773

申请日：2012-05-14

Applicant: Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

Inventor： Young-Ho Lee ,  Jae-Kwan Park ,  Jae-Hwang Sim ,  Sang-Yong Park

IPC: H01L21/467 ,  H01L27/02 ,  H01L21/033 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/762 ,  H01L23/544 ,  H01L27/115 ,  H01L27/105

CPC classification number: H01L27/0207 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.

Abstract translation: 制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。 第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。 蚀刻第一和第二掩模结构的蚀刻掩模图案以从第二掩模结构部分去除蚀刻掩模图案。 间隔件形成在第一和第二掩模结构的相对侧壁上。 第一掩模结构被选择性地从第一区域中的间隔物之间​​移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物，以及包括与第二掩模结构相对的侧壁间隔物的第二掩模图案 在第二区域中。

公开(公告)号：US08921233B2

公开(公告)日：2014-12-30

申请号：US13241788

申请日：2011-09-23

Applicant: Jae-hwang Sim ,  Min-chul Kim

Inventor： Jae-hwang Sim ,  Min-chul Kim

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/308 ,  H01L21/033 ,  H01L21/311 ,  H01L27/115

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548

Abstract: Some embodiments provide microelectronic fabrication methods in which a sacrificial pattern is formed on a substrate. A spacer formation layer is formed on the substrate, the spacer formation layer covering the sacrificial pattern. The spacer formation layer is etched to expose an upper surface of the sacrificial pattern and to leave at least one spacer on at least one sidewall of the sacrificial pattern. A first portion of the sacrificial pattern having a first width is removed while leaving intact a second portion of the sacrificial pattern having a second width greater than the first width to thereby form a composite mask pattern including the at least one spacer and a portion of the sacrificial layer. An underlying portion of the substrate is etched using the composite mask pattern as an etching mask.

Abstract translation: 一些实施例提供了微电子制造方法，其中在衬底上形成牺牲图案。 在衬底上形成间隔物形成层，间隔物形成层覆盖牺牲图案。 蚀刻间隔物形成层以暴露牺牲图案的上表面并且在牺牲图案的至少一个侧壁上留下至少一个间隔物。 消除具有第一宽度的牺牲图案的第一部分，同时保留牺牲图案的第二部分具有大于第一宽度的第二宽度，从而形成包括至少一个间隔物的复合掩模图案，并且部分 牺牲层。 使用复合掩模图案作为蚀刻掩模蚀刻衬底的下面部分。

公开(公告)号：US20140191405A1

公开(公告)日：2014-07-10

申请号：US14208456

申请日：2014-03-13

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

IPC: H01L23/528

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

Abstract translation: 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

公开(公告)号：US20140151777A1

公开(公告)日：2014-06-05

申请号：US14096195

申请日：2013-12-04

Applicant: Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

Inventor： Jae-Hwang Sim ,  Jinhyun Shin ,  Jong-Min Lee

IPC: H01L29/788

CPC classification number: H01L27/11524 ,  H01L21/764 ,  H01L29/42324

Abstract: Provided are a semiconductor memory device and a method of fabricating the same, the semiconductor memory device may include a semiconductor substrate with a first trench defining active regions in a first region and a second trench provided in a second region around the first region, a gate electrode provided on the first region to cross the active regions, a charge storing pattern disposed between the gate electrode and the active regions, a blocking insulating layer provided between the gate electrode and the charge storing pattern and extending over the first trench to define a first air gap in the first trench, and an insulating pattern provided spaced apart from a bottom surface of the second trench to define a second air gap in the second trench.

Abstract translation: 提供一种半导体存储器件及其制造方法，半导体存储器件可以包括半导体衬底，该半导体衬底具有限定第一区域中的有源区域的第一沟槽和设置在第一区域周围的第二区域中的第二沟槽，栅极 电极，设置在第一区域上以与有源区交叉，设置在栅电极和有源区之间的电荷存储图案，设置在栅电极和电荷存储图案之间并在第一沟槽上延伸以限定第一 第一沟槽中的空气间隙，以及设置成与第二沟槽的底表面间隔开的绝缘图案，以在第二沟槽中限定第二气隙。

公开(公告)号：US08598710B2

公开(公告)日：2013-12-03

申请号：US12950347

申请日：2010-11-19

Applicant: Yoonmoon Park ,  Jae-Hwang Sim ,  Se-Young Park ,  Keonsoo Kim ,  Jaehan Lee ,  Seungwon Seong

Inventor： Yoonmoon Park ,  Jae-Hwang Sim ,  Se-Young Park ,  Keonsoo Kim ,  Jaehan Lee ,  Seungwon Seong

IPC: H01L23/48

CPC classification number: H01L27/3223 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L27/11519 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate including a cell region and a core region adjacent to the cell region, active regions in the cell region and the core region, an interlayer insulating layer covering the active regions, upper cell contacts penetrating the interlayer insulating layer in the cell region, the upper cell contacts being adjacent to each other along a first direction and being electrically connected to the active regions, and core contacts penetrating the interlayer insulating layer in the active regions of the core region, the core contacts being adjacent to each other along the first direction and including upper connection core contacts electrically connected to the active regions, and dummy contacts adjacent to the upper connection core contacts, the dummy contacts being insulated from the active regions.

Abstract translation: 半导体器件包括：半导体衬底，包括单元区域和与单元区域相邻的芯区域，单元区域和芯区域中的有源区域，覆盖有源区域的层间绝缘层，穿过层间绝缘层的上部单元触点 电池区域，上电池触点沿着第一方向彼此相邻并且电连接到有源区域，并且芯触点穿透芯区域的有源区域中的层间绝缘层，芯触点与每个区域相邻 另一个沿着第一方向并且包括电连接到有源区的上连接芯触点，以及与上连接芯触点相邻的虚拟触头，虚拟触头与有源区绝缘。

公开(公告)号：US08541284B2

公开(公告)日：2013-09-24

申请号：US13302080

申请日：2011-11-22

Applicant: Jae-Hwang Sim

Inventor： Jae-Hwang Sim

IPC: H01L21/8242 ,  H01L21/76

CPC classification number: H01L29/788 ,  H01L21/76229 ,  H01L21/764

Abstract: A method of manufacturing a semiconductor device includes forming a plurality of strings spaced a first distance from each other, each string including first preliminary gate structures spaced a second distance, smaller than the first distance, between second preliminary gate structures, forming a first insulation layer to cover the first and second preliminary gate structures, forming an insulation layer structure to fill a space between the strings, forming a sacrificial layer pattern to partially fill spaces between first and second preliminary gate structures, removing a portion of the first insulation layer not covered by the sacrificial layer pattern to form a first insulation layer pattern, reacting portions of the first and second preliminary gate structures not covered by the first insulation layer pattern with a conductive layer to form gate structures, and forming a capping layer on the gate structures to form air gaps between the gate structures.

Abstract translation: 一种制造半导体器件的方法包括形成彼此间隔开第一距离的多个串，每个串包括在第二预栅结构之间间隔第二距离小于第一距离的第一预栅极结构，形成第一绝缘层 覆盖第一和第二预选栅极结构，形成绝缘层结构以填充串之间的空间，形成牺牲层图案以部分地填充第一和第二预选栅结构之间的空间，去除未覆盖的第一绝缘层的一部分 通过所述牺牲层图案以形成第一绝缘层图案，使未被所述第一绝缘层图案覆盖的所述第一和第二预选栅极结构的部分与导电层反应以形成栅极结构，并且在所述栅极结构上形成覆盖层 在门结构之间形成气隙。

公开(公告)号：US08436412B2

公开(公告)日：2013-05-07

申请号：US12824480

申请日：2010-06-28

Applicant: Yoon Moon Park ,  Jae Hwang Sim ,  Keon Soo Kim

Inventor： Yoon Moon Park ,  Jae Hwang Sim ,  Keon Soo Kim

IPC: H01L29/788 ,  G11C11/34 ,  G11C16/04

CPC classification number: H01L29/0657 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529

Abstract: A pattern structure for a semiconductor device includes a plurality of first patterns, each of the first patterns extending in a first direction in the shape of a line, neighboring first patterns being spaced apart from each other by a gap distance, the plurality of first patterns including a plurality of trenches in parallel with the line shapes, respective trenches being between neighboring first patterns, the plurality of trenches including long trenches and short trenches alternately arranged in a second direction substantially perpendicular to the first direction, and at least a second pattern, the second pattern being coplanar with the first pattern, end portions of the first patterns being connected to the second pattern.

公开(公告)号：US08318603B2

公开(公告)日：2012-11-27

申请号：US12653588

申请日：2009-12-16

Applicant: Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

Inventor： Young-Ho Lee ,  Jae-Hwang Sim ,  Sang-Yong Park ,  Kyung-Lyul Moon

IPC: H01L21/311

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76229 ,  H01L21/76816 ,  H01L21/76838 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11526 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region.

Abstract translation: 提供一种形成半导体器件的图案的方法，其中精细图案和大幅图案同时并且彼此相邻地形成。 在该方法中，在衬底上形成第一层以覆盖包括在衬底中的第一区域和第二区域。 同时形成覆盖第一区域中的第一层的一部分的阻挡图案和覆盖第二区域中的第一层的一部分的低密度大图案。 在第一层上形成多个牺牲掩模图案，并在第一区域中形成阻挡图案。 形成覆盖多个牺牲掩模图案的暴露侧壁的多个间隔物。 去除多个牺牲掩模图案。 通过使用多个间隔物和阻挡图案作为第一区域中的蚀刻掩模并且在第二区域中使用低密度大宽度图案作为蚀刻掩模，同时蚀刻第一和第二区域中的第一层。

公开(公告)号：US08310055B2

公开(公告)日：2012-11-13

申请号：US12645820

申请日：2009-12-23

Applicant: Young-ju Park ,  Jae-ho Min ,  Myeong-cheol Kim ,  Dong-chan Kim ,  Jae-hwang Sim

Inventor： Young-ju Park ,  Jae-ho Min ,  Myeong-cheol Kim ,  Dong-chan Kim ,  Jae-hwang Sim

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L23/522 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11531 ,  H01L27/11548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction, and the first direction is different from the second direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines via the second line portion of the corresponding conductive line; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction.

Abstract translation: 提供形成半导体器件的半导体器件和方法，其中同时形成多个图案以具有不同的宽度，并且使用双重图案化来增加一些区域的图案密度。 半导体器件包括多个导线，每条导线包括第一线部分和第二线部分，其中第一线部分在第一方向上在衬底上延伸，第二线部分从第一线部分的一端延伸到 第二方向，第一方向与第二方向不同; 多个接触焊盘，每个接触焊盘经由相应的导线的第二线部分与多条导线的相应导线连接; 以及多个虚设导电线，每个虚设导电线包括从所述多个接触焊盘的相应的接触焊盘延伸的第一虚设部分，与所述第二方向上的对应的第二线部分平行。

公开(公告)号：US20120252185A1

公开(公告)日：2012-10-04

申请号：US13470773

申请日：2012-05-14

Applicant: Young-Ho LEE ,  Jae-Kwan PARK ,  Jae-Hwang SIM ,  Sang-Yong PARK

Inventor： Young-Ho LEE ,  Jae-Kwan PARK ,  Jae-Hwang SIM ,  Sang-Yong PARK

IPC: H01L21/762 ,  H01L21/302 ,  H01L21/28

CPC classification number: H01L27/0207 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method of fabricating an integrated circuit device includes forming first and second mask structures on respective first and second regions of a feature layer. Each of the first and second mask structures includes a dual mask pattern and an etch mask pattern thereon having an etch selectivity relative to the dual mask pattern. The etch mask patterns of the first and second mask structures are etched to partially remove the etch mask pattern from the second mask structure. Spacers are formed on opposing sidewalls of the first and second mask structures. The first mask structure is selectively removed from between the spacers in the first region to define a first mask pattern including the opposing sidewall spacers with a void therebetween in the first region, and a second mask pattern including the opposing sidewall spacers with the second mask structure therebetween in the second region.

Abstract translation: 制造集成电路器件的方法包括在特征层的相应的第一和第二区域上形成第一和第二掩模结构。 第一和第二掩模结构中的每一个包括双掩模图案和其上具有相对于双掩模图案的蚀刻选择性的蚀刻掩模图案。 蚀刻第一和第二掩模结构的蚀刻掩模图案以从第二掩模结构部分去除蚀刻掩模图案。 间隔件形成在第一和第二掩模结构的相对侧壁上。 第一掩模结构被选择性地从第一区域中的间隔物之间​​移除，以限定第一掩模图案，其包括在第一区域中具有空隙的相对的侧壁间隔物，以及包括与第二掩模结构相对的侧壁间隔物的第二掩模图案 在第二区域中。