公开(公告)号：US20120129334A1

公开(公告)日：2012-05-24

申请号：US13365378

申请日：2012-02-03

Applicant: Hyun-Soo CHUNG ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

Inventor： Hyun-Soo CHUNG ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

IPC: H01L21/768

CPC classification number: H01L24/91 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.

Abstract translation: 提供半导体封装和制造半导体封装的方法。 半导体封装可以包括衬底，其包括芯片焊盘，电连接到芯片焊盘并且包括开口的再分布线。 半导体封装还可以包括外部端子连接部分和设置在开口处并电连接到重新分配线路的外部端子连接焊盘。 本发明的总体构思可以解决包含在再分布线中的金的成分被阻止扩散到相邻的凸块焊盘中以形成空隙或不期望的金属间化合物的问题。 在片上芯片结构中，下部芯片的多个凸起连接到上部芯片以提高片上芯片结构的可靠性，分集性和功能性。

公开(公告)号：US08735276B2

公开(公告)日：2014-05-27

申请号：US13365378

申请日：2012-02-03

Applicant: Hyun-Soo Chung ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

Inventor： Hyun-Soo Chung ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

IPC: H01L21/768

CPC classification number: H01L24/91 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.

Abstract translation: 提供半导体封装和制造半导体封装的方法。 半导体封装可以包括衬底，其包括芯片焊盘，电连接到芯片焊盘并且包括开口的再分布线。 半导体封装还可以包括外部端子连接部分和设置在开口处并电连接到重新分配线路的外部端子连接焊盘。 本发明的总体构思可以解决包含在再分布线中的金的成分被阻止扩散到相邻的凸块焊盘中以形成空隙或不期望的金属间化合物的问题。 在片上芯片结构中，下部芯片的多个凸起连接到上部芯片以提高片上芯片结构的可靠性，分集性和功能性。

公开(公告)号：US20090184411A1

公开(公告)日：2009-07-23

申请号：US12353501

申请日：2009-01-14

Applicant: Hyun-Soo CHUNG ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

Inventor： Hyun-Soo CHUNG ,  Jae-Shin Cho ,  Dong-Ho Lee ,  Dong-Hyeon Jang ,  Seong-Deok Hwang ,  Seung-Duk Baek

IPC: H01L23/48

CPC classification number: H01L24/91 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48463 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure.

Abstract translation: 提供半导体封装和制造半导体封装的方法。 半导体封装可以包括衬底，其包括芯片焊盘，电连接到芯片焊盘并且包括开口的再分布线。 半导体封装还可以包括外部端子连接部分和设置在开口处并电连接到重新分配线路的外部端子连接焊盘。 本发明的总体构思可以解决包含在再分布线中的金的成分被阻止扩散到相邻的凸块焊盘中以形成空隙或不期望的金属间化合物的问题。 在片上芯片结构中，下部芯片的多个凸起连接到上部芯片以提高片上芯片结构的可靠性，分集性和功能性。

公开(公告)号：US07969024B2

公开(公告)日：2011-06-28

申请号：US12453103

申请日：2009-04-29

Applicant: Hyun-soo Chung ,  Jae-shin Cho ,  Seong-deok Hwang ,  Jum-gon Kim ,  Ki-hyuk Kim

Inventor： Hyun-soo Chung ,  Jae-shin Cho ,  Seong-deok Hwang ,  Jum-gon Kim ,  Ki-hyuk Kim

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/49811 ,  H01L23/525 ,  H01L23/53252 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/325 ,  H05K2201/10348 ,  H05K2201/10977 ,  H01L2924/00014

Abstract: A semiconductor package with improved joint reliability and a method of fabricating the semiconductor package are disclosed. A conductive connector may be formed on a surface of a semiconductor wafer on which semiconductor devices may be arranged. A first insulating layer including a first opening through which a portion of the connection pad is exposed may be formed on the connection pad and the semiconductor wafer. A rewiring line electrically connected to an exposed portion of the connection pad may be formed on the first insulating layer. A second insulating layer including a second opening through which a portion of the rewiring line is exposed may be formed on the rewiring line and the first insulating layer. A connection terminal including one or more entangled wires may be formed on an exposed portion of the rewiring line so as to be electrically connected to the rewiring line.

Abstract translation: 公开了一种具有改进的接头可靠性的半导体封装以及制造半导体封装的方法。 可以在其上可以布置半导体器件的半导体晶片的表面上形成导电连接器。 包括连接焊盘的一部分露出的第一开口的第一绝缘层可以形成在连接焊盘和半导体晶片上。 电连接到连接焊盘的暴露部分的再布线可以形成在第一绝缘层上。 可以在重新配线和第一绝缘层上形成第二绝缘层，该第二绝缘层包括第二开口，重新布线的一部分暴露在第二开口中。 包括一个或多个缠结线的连接端子可以形成在重新布线的暴露部分上，以便电连接到重新布线。

公开(公告)号：US20090315177A1

公开(公告)日：2009-12-24

申请号：US12453103

申请日：2009-04-29

Applicant: Hyun-soo Chung ,  Jae-shin Cho ,  Seong-deok Hwang ,  Jum-gon Kim ,  Ki-hyuk Kim

Inventor： Hyun-soo Chung ,  Jae-shin Cho ,  Seong-deok Hwang ,  Jum-gon Kim ,  Ki-hyuk Kim

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L23/525 ,  H01L23/53252 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05155 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/111 ,  H01L2224/11334 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/325 ,  H05K2201/10348 ,  H05K2201/10977 ,  H01L2924/00014

Abstract: A semiconductor package with improved joint reliability and a method of fabricating the semiconductor package are disclosed. A conductive connector may be formed on a surface of a semiconductor wafer on which semiconductor devices may be arranged. A first insulating layer including a first opening through which a portion of the connection pad is exposed may be formed on the connection pad and the semiconductor wafer. A rewiring line electrically connected to an exposed portion of the connection pad may be formed on the first insulating layer. A second insulating layer including a second opening through which a portion of the rewiring line is exposed may be formed on the rewiring line and the first insulating layer. A connection terminal including one or more entangled wires may be formed on an exposed portion of the rewiring line so as to be electrically connected to the rewiring line.

Abstract translation: 公开了一种具有改进的接头可靠性的半导体封装以及制造半导体封装的方法。 可以在其上可以布置半导体器件的半导体晶片的表面上形成导电连接器。 包括连接焊盘的一部分露出的第一开口的第一绝缘层可以形成在连接焊盘和半导体晶片上。 电连接到连接焊盘的暴露部分的再布线可以形成在第一绝缘层上。 可以在重新配线和第一绝缘层上形成第二绝缘层，该第二绝缘层包括第二开口，重新布线的一部分暴露在第二开口中。 包括一个或多个缠结线的连接端子可以形成在重新布线的暴露部分上，以便电连接到重新布线。