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    VIA STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    2.
    发明申请
    VIA STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
    通过半导体器件的结构及其制造方法

    公开(公告)号：US20110248283A1

    公开(公告)日：2011-10-13

    申请号：US13081140

    申请日：2011-04-06

    申请人： Jianjun Cao ,  Robert Beach ,  Alexander Lidow ,  Alana Nakata

    发明人： Jianjun Cao ,  Robert Beach ,  Alexander Lidow ,  Alana Nakata

    IPC分类号： H01L29/20 ,  H01L21/28

    CPC分类号： H01L29/41725 ,  H01L29/2003 ,  H01L29/42312

    摘要： Semiconductor devices, such as GaN HEMT and HFET devices, and methods of forming such devices, with a via that provides an electrical connection between a contact and a corresponding external contact pad. Embodiments include semiconductor devices with a via extending through a dielectric material to connect a gate to a corresponding external contact pad, and semiconductor devices with a via extending through a dielectric material to connect an Ohmic contact and a corresponding external contact pad. Embodiments also include semiconductor devices with a via connecting an external contact pad to a gate that is formed above a dielectric material.

    摘要翻译： 半导体器件，例如GaN HEMT和HFET器件，以及形成这种器件的方法，具有通孔，其提供触点和对应的外部接触焊盘之间的电连接。 实施例包括具有延伸穿过电介质材料以将栅极连接到相应的外部接触焊盘的通孔的半导体器件，以及具有延伸穿过介电材料以连接欧姆接触和相应的外部接触焊盘的通孔的半导体器件。 实施例还包括具有将外部接触焊盘连接到形成在电介质材料上方的栅极的通孔的半导体器件。

    ENHANCEMENT MODE GaN HEMT DEVICE AND METHOD FOR FABRICATING THE SAME
    3.
    发明申请
    ENHANCEMENT MODE GaN HEMT DEVICE AND METHOD FOR FABRICATING THE SAME 有权
    增强型GaN HEMT器件及其制造方法

    公开(公告)号：US20100258843A1

    公开(公告)日：2010-10-14

    申请号：US12756960

    申请日：2010-04-08

    申请人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao ,  Guang Yuan Zhao

    发明人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao ,  Guang Yuan Zhao

    IPC分类号： H01L29/778 ,  H01L21/335

    CPC分类号： H01L29/778 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786

    摘要： An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.

    摘要翻译： 一种增强型GaN晶体管及其形成方法。 增强型GaN晶体管包括衬底，过渡层，由III氮化物材料构成的缓冲层，由III氮化物材料构成的阻挡层，漏极和源极接触，含有受体型掺杂元素的栅III-V族化合物， 和栅极金属，其中栅极III-V化合物和栅极金属形成有单独的光掩模工艺以进行自对准，并且栅极金属的底部和栅极化合物的顶部具有相同的尺寸。 增强型GaN晶体管还可以具有由欧姆金属制成的场板，其中通过单个光掩模工艺形成漏极欧姆金属，源欧姆金属和场板。

    Power MOSFET with ultra-deep base and reduced on resistance
    10.
    发明授权
    Power MOSFET with ultra-deep base and reduced on resistance 有权
    功率MOSFET具有超深基极和降低导通电阻

    公开(公告)号：US06639276B2

    公开(公告)日：2003-10-28

    申请号：US10187580

    申请日：2002-07-01

    申请人： Kyle Spring ,  Jianjun Cao

    发明人： Kyle Spring ,  Jianjun Cao

    IPC分类号： H01L31113

    CPC分类号： H01L29/7802 ,  H01L21/2815 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/42368 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/66719

    摘要： A power semiconductor device formed of a substrate of a first conductivity type, an epitaxial layer of a first conductivity type formed on a surface of the substrate, a plurality of lightly doped spaced base regions of a second conductivity type formed to a first predetermined depth in the epitaxial layer with common conduction regions between the base regions, a plurality of highly doped source regions of the first conductivity type formed in the lightly doped base regions, invertible channel regions disposed between the source regions and the common conduction regions, deep implanted junctions of the second conductivity type formed in the epitaxial layer under the base regions extending between the first predetermined depth and a second predetermined depth, gate electrodes insulated from the invertible channels by an insulation layer formed over the invertible channels, and thick insulation spacers disposed over at least a portion of the common conduction regions.

    摘要翻译： 一种由第一导电类型的衬底形成的功率半导体器件，形成在衬底的表面上的第一导电类型的外延层，第二导电类型的多个轻掺杂间隔的基极区域形成为第一预定深度 在基极区域之间具有共同导电区域的外延层，形成在轻掺杂基极区域中的第一导电类型的多个高掺杂源极区域，设置在源区域和公共导电区域之间的可逆沟道区域， 形成在第一预定深度和第二预定深度之间的基底区域之下的外延层中的第二导电类型，通过形成在可逆通道上的绝缘层与可逆通道绝缘的栅极电极以及至少设置在绝缘层上的厚绝缘间隔物 一部分共同导电区域。