公开(公告)号：US07482654B2

公开(公告)日：2009-01-27

申请号：US11110467

申请日：2005-04-20

申请人： Jianjun Cao ,  Timothy D. Henson ,  Naresh Thapar ,  Paul Harvey ,  David Kent

发明人： Jianjun Cao ,  Timothy D. Henson ,  Naresh Thapar ,  Paul Harvey ,  David Kent

IPC分类号： H01L29/76

CPC分类号： H01L29/7828 ,  H01L29/407 ,  H01L29/66666

摘要： A power semiconductor device which includes a source field electrode, and at least one insulated gate electrode adjacent a respective side of the source field electrode, the source field electrode and the gate electrode being disposed in a common trench, and a method for fabricating the device.

摘要翻译： 一种功率半导体器件，包括源极电极和邻近源极场电极的相应侧的至少一个绝缘栅电极，源极场电极和栅电极设置在公共沟槽中，以及制造该器件的方法 。

公开(公告)号：US08860194B2

公开(公告)日：2014-10-14

申请号：US13666854

申请日：2012-11-01

申请人： Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

发明人： Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

IPC分类号： H01L23/495

CPC分类号： H01L25/18 ,  H01L25/072 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/13091 ,  H01L2924/16251 ,  H02M3/1588 ,  Y02B70/1466 ,  H01L2924/00

摘要： One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

摘要翻译： 一个示例性的公开的实施例包括包括垂直导通控制晶体管和垂直导通同步晶体管的半导体封装。 垂直传导控制晶体管可以包括控制源，控制栅极和控制漏极，其都可从底表面接近，从而使电和直接表面安装到支撑表面。 垂直导通同步晶体管可以包括顶表面上的同步漏极，其可以连接到耦合到支撑表面的导电夹子。 导电夹子也可以热耦合到控制晶体管。 因此，晶体管的所有端子容易通过支撑表面接近，并且诸如降压转换器电源相的功率电路可以通过支撑表面的迹线来实现。 可选地，驱动器IC可以集成到封装中，并且散热器可以附接到导电夹子。

公开(公告)号：US20110284950A1

公开(公告)日：2011-11-24

申请号：US12800662

申请日：2010-05-20

申请人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Kapil Kelkar ,  Niraj Ranjan

发明人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Kapil Kelkar ,  Niraj Ranjan

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L21/265 ,  H01L21/30625 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66734

摘要： Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed.

摘要翻译： 公开了一种制造浅沟槽场效应晶体管（沟槽FET）的方法。 该方法包括在第一导电类型的半导体衬底内形成沟槽，沟槽包括侧壁和底部。 该方法还包括在沟槽中形成基本上均匀的栅极电介质，以及在所述沟槽内和所述栅极电介质上方形成栅电极。 该方法还包括在形成沟槽之后掺杂半导体衬底以形成第二导电类型的沟道区。 在一个实施例中，在形成栅极电介质之后并在形成栅电极之后执行掺杂步骤。 在另一个实施例中，掺杂步骤在形成栅极电介质之后，但在形成栅电极之前进行。 还公开了通过本发明方法形成的结构。

公开(公告)号：US08698232B2

公开(公告)日：2014-04-15

申请号：US12655668

申请日：2010-01-04

申请人： Aram Arzumanyan ,  Timothy D. Henson ,  Ling Ma

发明人： Aram Arzumanyan ,  Timothy D. Henson ,  Ling Ma

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

摘要： According to one embodiment, a semiconductor device including a voltage controlled termination structure comprises an active area including a base region of a first conductivity type formed in a semiconductor body of a second conductivity type formed over a first major surface of a substrate of the second conductivity type, a termination region formed in the semiconductor body adjacent the active area and including the voltage controlled termination structure. The voltage controlled termination structure includes an electrode electrically connected to a terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a gate terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a source terminal of the semiconductor device.

摘要翻译： 根据一个实施例，包括电压控制终端结构的半导体器件包括有源区，该有源区包括形成在第二导电类型的半导体本体中的第一导电类型的基极区，形成在第二导电性的衬底的第一主表面上 类型，形成在与有源区相邻的半导体本体中并且包括电压控制的端接结构的端接区。 电压控制终端结构包括电连接到半导体器件的端子的电极。 在一个实施例中，电压控制终端结构的电极电连接到半导体器件的栅极端子。 在一个实施例中，电压控制终端结构的电极电连接到半导体器件的源极端子。

公开(公告)号：US08536645B2

公开(公告)日：2013-09-17

申请号：US13031505

申请日：2011-02-21

申请人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Martin Carroll

发明人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Martin Carroll

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

摘要： According to an exemplary embodiment, a trench field-effect transistor (trench FET) includes a trench formed in a semiconductor substrate, the trench including a gate dielectric disposed therein. A source region is disposed adjacent the trench. The trench FET also has a gate electrode including a lower portion disposed in the trench and a proud portion extending laterally over the source region. A silicide source contact can extend vertically along a sidewall of the source region. Also, a portion of the gate dielectric can extend laterally over the semiconductor substrate. The trench FET can further include a silicide gate contact formed over the proud portion of the gate electrode.

摘要翻译： 根据示例性实施例，沟槽场效应晶体管（沟槽FET）包括形成在半导体衬底中的沟槽，沟槽包括设置在其中的栅极电介质。 源极区域邻近沟槽设置。 沟槽FET还具有包括设置在沟槽中的下部的栅电极和在源极区域上横向延伸的骄傲部分。 硅化物源接触件可以沿着源极区域的侧壁垂直延伸。 此外，栅极电介质的一部分可以在半导体衬底上横向延伸。 沟槽FET还可以包括形成在栅电极的骄傲部分上的硅化物栅极接触。

公开(公告)号：US20120211825A1

公开(公告)日：2012-08-23

申请号：US13031505

申请日：2011-02-21

申请人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Martin Carroll

发明人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Martin Carroll

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

摘要： According to an exemplary embodiment, a trench field-effect transistor (trench FET) includes a trench formed in a semiconductor substrate, the trench including a gate dielectric disposed therein. A source region is disposed adjacent the trench. The trench FET also has a gate electrode including a lower portion disposed in the trench and a proud portion extending laterally over the source region. A silicide source contact can extend vertically along a sidewall of the source region. Also, a portion of the gate dielectric can extend laterally over the semiconductor substrate. The trench FET can further include a silicide gate contact formed over the proud portion of the gate electrode.

摘要翻译： 根据示例性实施例，沟槽场效应晶体管（沟槽FET）包括形成在半导体衬底中的沟槽，沟槽包括设置在其中的栅极电介质。 源极区域邻近沟槽设置。 沟槽FET还具有包括设置在沟槽中的下部的栅电极和在源极区域上横向延伸的骄傲部分。 硅化物源接触件可以沿着源极区域的侧壁垂直延伸。 此外，栅极电介质的一部分可以在半导体衬底上横向延伸。 沟槽FET还可以包括形成在栅电极的骄傲部分上的硅化物栅极接触。

公开(公告)号：US20110163373A1

公开(公告)日：2011-07-07

申请号：US12655668

申请日：2010-01-04

申请人： Aram Arzumanyan ,  Timothy D. Henson ,  Ling Ma

发明人： Aram Arzumanyan ,  Timothy D. Henson ,  Ling Ma

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7813

摘要： According to one embodiment, a semiconductor device including a voltage controlled termination structure comprises an active area including a base region of a first conductivity type formed in a semiconductor body of a second conductivity type formed over a first major surface of a substrate of the second conductivity type, a termination region formed in the semiconductor body adjacent the active area and including the voltage controlled termination structure. The voltage controlled termination structure includes an electrode electrically connected to a terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a gate terminal of the semiconductor device. In one embodiment, the electrode of the voltage controlled termination structure is electrically connected to a source terminal of the semiconductor device.

摘要翻译： 根据一个实施例，包括电压控制终端结构的半导体器件包括有源区，该有源区包括形成在第二导电类型的半导体本体中的第一导电类型的基极区，形成在第二导电性的衬底的第一主表面上 类型，形成在与有源区相邻的半导体本体中并且包括电压控制的端接结构的端接区。 电压控制终端结构包括电连接到半导体器件的端子的电极。 在一个实施例中，电压控制终端结构的电极电连接到半导体器件的栅极端子。 在一个实施例中，电压控制终端结构的电极电连接到半导体器件的源极端子。

公开(公告)号：US20140118032A1

公开(公告)日：2014-05-01

申请号：US13666854

申请日：2012-11-01

申请人： Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

发明人： Ling Ma ,  Andrew N. Sawle ,  David Paul Jones ,  Timothy D. Henson ,  Niraj Ranjan ,  Vijay Viswanathan ,  Omar Hassen

IPC分类号： H02M3/155

CPC分类号： H01L25/18 ,  H01L25/072 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/13091 ,  H01L2924/16251 ,  H02M3/1588 ,  Y02B70/1466 ,  H01L2924/00

摘要： One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

摘要翻译： 一个示例性的公开的实施例包括包括垂直导通控制晶体管和垂直导通同步晶体管的半导体封装。 垂直传导控制晶体管可以包括控制源，控制栅极和控制漏极，其都可从底表面接近，从而使电和直接表面安装到支撑表面。 垂直导通同步晶体管可以包括顶表面上的同步漏极，其可连接到耦合到支撑表面的导电夹子。 导电夹子也可以热耦合到控制晶体管。 因此，晶体管的所有端子容易通过支撑表面接近，并且诸如降压转换器电源相的功率电路可以通过支撑表面的迹线来实现。 可选地，驱动器IC可以集成到封装中，并且散热器可以附接到导电夹子。

公开(公告)号：US09653597B2

公开(公告)日：2017-05-16

申请号：US12800662

申请日：2010-05-20

申请人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Kapil Kelkar ,  Niraj Ranjan ,  Igor Bol

发明人： Timothy D. Henson ,  Ling Ma ,  Hugo Burke ,  David P. Jones ,  Kapil Kelkar ,  Niraj Ranjan ,  Igor Bol

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/265 ,  H01L21/30625 ,  H01L29/0878 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66734

摘要： Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed.

公开(公告)号：US07554153B2

公开(公告)日：2009-06-30

申请号：US11715223

申请日：2007-03-07

申请人： Timothy D. Henson

发明人： Timothy D. Henson

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368

摘要： A power semiconductor device which includes an implant region in the base region thereof to reduce Qgd.

摘要翻译： 一种功率半导体器件，其在其基极区域中包括植入区域以减少Qgd。