公开(公告)号：US08823012B2

公开(公告)日：2014-09-02

申请号：US13403400

申请日：2012-02-23

申请人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao ,  Guang Yuan Zhao ,  Robert Strittmatter ,  Fang Chang Liu

发明人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao ,  Guang Yuan Zhao ,  Robert Strittmatter ,  Fang Chang Liu

IPC分类号： H01L21/48 ,  H01L21/02 ,  H01L29/20 ,  H01L33/00

CPC分类号： H01L21/0254 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786 ,  H01L33/007

摘要： Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability.

摘要翻译： 具有栅极间隔物，栅极金属材料和自对准的栅极化合物的增强型GaN器件及其形成方法。 使用单个光掩模对材料进行图案化和蚀刻，这降低了制造成本。 栅极间隔物和栅极化合物的界面比电介质膜和栅极化合物的界面具有更低的泄漏，从而减少栅极泄漏。 此外，使用欧姆接触金属层作为场板，以减轻掺杂III-V栅极化合物角向漏极接触的电场，这导致较低的栅极漏电流和改善的栅极可靠性。

公开(公告)号：US20100258848A1

公开(公告)日：2010-10-14

申请号：US12756906

申请日：2010-04-08

申请人： Alexander Lidow ,  Robert Beach ,  Jianjun Cao ,  Alana Nakata ,  Guang Yuan Zhao

发明人： Alexander Lidow ,  Robert Beach ,  Jianjun Cao ,  Alana Nakata ,  Guang Yuan Zhao

IPC分类号： H01L29/78 ,  H01L29/772

CPC分类号： H01L29/802 ,  H01L29/2003 ,  H01L29/66522

摘要： A MISFET, such as a GaN transistor, with low gate leakage. In one embodiment, the gate leakage is reduced with a compensated GaN layer below the gate contact and above the barrier layer. In another embodiment, the gate leakage is reduced by employing a semi-insulating layer below the gate contact and above the barrier layer.

摘要翻译： 具有低栅极泄漏的MISFET，例如GaN晶体管。 在一个实施例中，栅极泄漏随着栅极接触下方的补偿GaN层和势垒层上方而减小。 在另一个实施例中，通过在栅极接触之下和阻挡层之上采用半绝缘层来减小栅极泄漏。

公开(公告)号：US20100258844A1

公开(公告)日：2010-10-14

申请号：US12756975

申请日：2010-04-08

申请人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao

发明人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao

IPC分类号： H01L29/772 ,  H01L23/367 ,  H01L23/488

CPC分类号： H01L23/3192 ,  H01L23/3178 ,  H01L23/367 ,  H01L23/3672 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0657 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41725 ,  H01L29/7787 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device.

摘要翻译： 一种半导体器件，包括硅衬底，化合物半导体材料，硅衬底和化合物半导体材料之间的绝缘材料，以及包括电连接装置的顶表面和钝化材料，其中钝化材料是氮化硅，二氧化硅 ，或两者的组合。 本发明通过包含AlN晶种层来电绝缘器件的硅衬底，消除了散热器与表面安装器件背面之间的厚电绝缘体的需要。 器件的侧壁也与器件的有源区域电隔离。

公开(公告)号：US20110248283A1

公开(公告)日：2011-10-13

申请号：US13081140

申请日：2011-04-06

申请人： Jianjun Cao ,  Robert Beach ,  Alexander Lidow ,  Alana Nakata

发明人： Jianjun Cao ,  Robert Beach ,  Alexander Lidow ,  Alana Nakata

IPC分类号： H01L29/20 ,  H01L21/28

CPC分类号： H01L29/41725 ,  H01L29/2003 ,  H01L29/42312

摘要： Semiconductor devices, such as GaN HEMT and HFET devices, and methods of forming such devices, with a via that provides an electrical connection between a contact and a corresponding external contact pad. Embodiments include semiconductor devices with a via extending through a dielectric material to connect a gate to a corresponding external contact pad, and semiconductor devices with a via extending through a dielectric material to connect an Ohmic contact and a corresponding external contact pad. Embodiments also include semiconductor devices with a via connecting an external contact pad to a gate that is formed above a dielectric material.

摘要翻译： 半导体器件，例如GaN HEMT和HFET器件，以及形成这种器件的方法，具有通孔，其提供触点和对应的外部接触焊盘之间的电连接。 实施例包括具有延伸穿过电介质材料以将栅极连接到相应的外部接触焊盘的通孔的半导体器件，以及具有延伸穿过介电材料以连接欧姆接触和相应的外部接触焊盘的通孔的半导体器件。 实施例还包括具有将外部接触焊盘连接到形成在电介质材料上方的栅极的通孔的半导体器件。

公开(公告)号：US20100258843A1

公开(公告)日：2010-10-14

申请号：US12756960

申请日：2010-04-08

申请人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao ,  Guang Yuan Zhao

发明人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao ,  Guang Yuan Zhao

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/778 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786

摘要： An enhancement-mode GaN transistor and a method of forming it. The enhancement-mode GaN transistor includes a substrate, transition layers, a buffer layer comprised of a III Nitride material, a barrier layer comprised of a III Nitride material, drain and source contacts, a gate III-V compound containing acceptor type dopant elements, and a gate metal, where the gate III-V compound and the gate metal are formed with a single photo mask process to be self-aligned and the bottom of the gate metal and the top of the gate compound have the same dimension. The enhancement mode GaN transistor may also have a field plate made of Ohmic metal, where a drain Ohmic metal, a source Ohmic metal, and the field plate are formed by a single photo mask process.

摘要翻译： 一种增强型GaN晶体管及其形成方法。 增强型GaN晶体管包括衬底，过渡层，由III氮化物材料构成的缓冲层，由III氮化物材料构成的阻挡层，漏极和源极接触，含有受体型掺杂元素的栅III-V族化合物， 和栅极金属，其中栅极III-V化合物和栅极金属形成有单独的光掩模工艺以进行自对准，并且栅极金属的底部和栅极化合物的顶部具有相同的尺寸。 增强型GaN晶体管还可以具有由欧姆金属制成的场板，其中通过单个光掩模工艺形成漏极欧姆金属，源欧姆金属和场板。

公开(公告)号：US20100258842A1

公开(公告)日：2010-10-14

申请号：US12756940

申请日：2010-04-08

申请人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao ,  Guang Yuan Zhao

发明人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao ,  Guang Yuan Zhao

IPC分类号： H01L29/80

CPC分类号： H01L29/7787 ,  H01L29/1066 ,  H01L29/2003

摘要： An enhancement mode GaN transistor having a gate pGaN structure having a thickness which avoids dielectric failure. In one embodiment, this thickness is in the range of 400 Å to 900 Å. In a preferred embodiment, the thickness is 600 Å.

摘要翻译： 具有栅极pGaN结构的增强型GaN晶体管，具有避免电介质破坏的厚度。 在一个实施例中，该厚度在400至900的范围内。 在优选实施例中，厚度为600埃。

公开(公告)号：US09607876B2

公开(公告)日：2017-03-28

申请号：US13325735

申请日：2011-12-14

申请人： Alexander Lidow ,  Jianjun Cao ,  Robert Beach ,  Johan Strydom ,  Alana Nakata ,  Guang Y. Zhao

发明人： Alexander Lidow ,  Jianjun Cao ,  Robert Beach ,  Johan Strydom ,  Alana Nakata ,  Guang Y. Zhao

IPC分类号： H01L21/74 ,  H01L21/761 ,  H01L21/762 ,  H01L29/732 ,  H01L29/778 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/085 ,  H01L29/20

CPC分类号： H01L21/743 ,  H01L21/761 ,  H01L21/76283 ,  H01L21/8252 ,  H01L21/8258 ,  H01L23/535 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/085 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/732 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7827 ,  H01L29/88 ,  H01L2924/0002 ,  H01L2924/00

摘要： Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

公开(公告)号：US08969918B2

公开(公告)日：2015-03-03

申请号：US12756940

申请日：2010-04-08

申请人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao ,  Guang Yuan Zhao

发明人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao ,  Guang Yuan Zhao

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L29/1066 ,  H01L29/2003

摘要： An enhancement mode GaN transistor having a gate pGaN structure having a thickness which avoids dielectric failure. In one embodiment, this thickness is in the range of 400 Å to 900 Å. In a preferred embodiment, the thickness is 600 Å.

摘要翻译： 具有栅极pGaN结构的增强型GaN晶体管，具有避免电介质破坏的厚度。 在一个实施例中，该厚度在400至900的范围内。 在优选实施例中，厚度为600埃。

公开(公告)号：US20120193688A1

公开(公告)日：2012-08-02

申请号：US13362669

申请日：2012-01-31

申请人： Alexander Lidow ,  Jianjun Cao ,  Robert Beach ,  Robert Strittmatter ,  Guang Y. Zhao ,  Alana Nakata

发明人： Alexander Lidow ,  Jianjun Cao ,  Robert Beach ,  Robert Strittmatter ,  Guang Y. Zhao ,  Alana Nakata

IPC分类号： H01L29/768 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L21/26546 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787

摘要： A self-aligned transistor gate structure that includes an ion-implanted portion of gate material surrounded by non-implanted gate material on each side. The gate structure may be formed, for example, by applying a layer of GaN material over an AlGaN barrier layer and implanting a portion of the GaN layer to create the gate structure that is laterally surrounded by the GaN layer.

摘要翻译： 一种自对准的晶体管栅极结构，其包括在每侧由非植入栅极材料包围的栅极材料的离子注入部分。 栅极结构可以例如通过在AlGaN阻挡层上施加GaN材料层并且注入GaN层的一部分以形成由GaN层横向包围的栅极结构来形成。

公开(公告)号：US08785974B2

公开(公告)日：2014-07-22

申请号：US12756975

申请日：2010-04-08

申请人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao

发明人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao

IPC分类号： H01L29/772 ,  H01L23/367

CPC分类号： H01L23/3192 ,  H01L23/3178 ,  H01L23/367 ,  H01L23/3672 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0657 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41725 ,  H01L29/7787 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device.

摘要翻译： 一种半导体器件，包括硅衬底，化合物半导体材料，硅衬底和化合物半导体材料之间的绝缘材料，以及包括电连接装置的顶表面和钝化材料，其中钝化材料是氮化硅，二氧化硅 ，或两者的组合。 本发明通过包含AlN晶种层来电绝缘器件的硅衬底，消除了散热器与表面安装器件背面之间的厚电绝缘体的需要。 器件的侧壁也与器件的有源区域电隔离。