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    Nonvolatile memory device and method for controlling word line or bit line thereof
    1.
    发明授权
    Nonvolatile memory device and method for controlling word line or bit line thereof 有权
    用于控制字线或其位线的非易失性存储器件和方法

    公开(公告)号：US08305806B2

    公开(公告)日：2012-11-06

    申请号：US12659690

    申请日：2010-03-17

    Applicant: Joon-Yong Choi ,  Byunggil Choi ,  Yu Hwan Ro ,  Yong-Jun Lee

    Inventor： Joon-Yong Choi ,  Byunggil Choi ,  Yu Hwan Ro ,  Yong-Jun Lee

    IPC: G11C16/04

    CPC classification number: G11C16/08

    Abstract: A nonvolatile memory device includes global selection lines, local selection lines, a first selection circuit, and a second selection circuit. The local lines correspond respectively to the global selection lines. The first selection circuit is configured to connect to the global selection lines to select the global selection lines. The second selection circuit is connected between the global selection lines and the local selection lines and is configured to select the local selection lines. The first selection circuit is configured to select at least one global selection line, and the second selection circuit is configured to select the local selection lines corresponding to the selected global selection line while the at least one global selection line is continuously activated.

    Abstract translation: 非易失性存储器件包括全局选择线，局部选择线，第一选择电路和第二选择电路。 本地线分别对应于全局选择线。 第一选择电路被配置为连接到全局选择线以选择全局选择线。 第二选择电路连接在全局选择线和本地选择线之间，并被配置为选择本地选择线。 第一选择电路被配置为选择至少一个全局选择线，并且第二选择电路被配置为在连续激活至少一个全局选择线的同时选择与所选择的全局选择线对应的本地选择线。

    Memory system including a resistance variable memory device
    2.
    发明授权
    Memory system including a resistance variable memory device 有权
    存储器系统包括电阻变量存储器件

    公开(公告)号：US07668007B2

    公开(公告)日：2010-02-23

    申请号：US12124523

    申请日：2008-05-21

    Applicant: Byung-Gil Choi ,  Woo-Yeong Cho ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    Inventor： Byung-Gil Choi ,  Woo-Yeong Cho ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    IPC: G11C11/00

    CPC classification number: G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

    Abstract: A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.

    Abstract translation: 存储器系统包括电阻可变存储器件和用于控制电阻变化存储器件的存储器控​​制器。 电阻可变存储器件包括连接到位线的存储单元，适于从外部提供的电源电压产生高电压的高压电路，其中高电压高于电源电压，预充电电路适于充电 位线到电源电压并进一步将位线充电到高电压，偏置电路适于使用高电压向位线提供读取电流;以及读出放大器，其适于使用来检测位线的电压电平 高电压。

    RESISTANCE VARIABLE MEMORY DEVICE AND READ METHOD THEREOF
    3.
    发明申请
    RESISTANCE VARIABLE MEMORY DEVICE AND READ METHOD THEREOF 有权
    电阻可变存储器件及其读取方法

    公开(公告)号：US20080232161A1

    公开(公告)日：2008-09-25

    申请号：US12124523

    申请日：2008-05-21

    Applicant: Byung-Gil Choi ,  Woo-Yeong Cho ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    Inventor： Byung-Gil Choi ,  Woo-Yeong Cho ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    IPC: G11C11/00

    CPC classification number: G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

    Abstract: A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.

    Abstract translation: 存储器系统包括电阻可变存储器件和用于控制电阻变化存储器件的存储器控​​制器。 电阻可变存储器件包括连接到位线的存储单元，适于从外部提供的电源电压产生高电压的高压电路，其中高电压高于电源电压，预充电电路适于充电 位线到电源电压并进一步将位线充电到高电压，偏置电路适于使用高电压向位线提供读取电流;以及读出放大器，其适于使用来检测位线的电压电平 高电压。

    Variable resistance memory device and method of manufacturing the same
    4.
    发明授权
    Variable resistance memory device and method of manufacturing the same 有权
    可变电阻存储器件及其制造方法

    公开(公告)号：US08116129B2

    公开(公告)日：2012-02-14

    申请号：US12872876

    申请日：2010-08-31

    Applicant: Yu-hwan Ro ,  Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh

    Inventor： Yu-hwan Ro ,  Byung-gil Choi ,  Woo-yeong Cho ,  Hyung-rok Oh

    IPC: G11C11/00

    CPC classification number: G11C5/063 ,  G11C13/00 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/24 ,  Y10S977/754

    Abstract: A variable resistance memory device includes a substrate, a plurality of active lines formed on the substrate, are uniformly separated, and extend in a first direction, a plurality of switching devices formed on the active lines and are separated from one another, a plurality of variable resistance devices respectively formed on and connected to the switching devices, a plurality of local bit lines formed on the variable resistance devices, are uniformly separated, extend in a second direction, and are connected to the variable resistance devices, a plurality of local word lines formed on the local bit lines, are uniformly separated, and extend in the first direction, a plurality of global bit lines formed on the local word lines, are uniformly separated, and extend in the second direction, and a plurality of global word lines formed on the global bit lines, are uniformly separated, and extend in the first direction.

    Abstract translation: 一种可变电阻存储器件，包括衬底，形成在衬底上的多个有源线，被均匀地分离并沿着第一方向延伸，多个开关器件形成在有源线上并彼此分离，多个 分别形成在开关装置上并连接到开关装置的可变电阻装置，形成在可变电阻装置上的多个局部位线被均匀分离，在第二方向上延伸，并且连接到可变电阻装置，多个局部字 形成在局部位线上的线被均匀地分离，并且在第一方向上延伸，形成在局部字线上的多个全局位线被均匀分离，并且在第二方向上延伸，并且多个全局字线 形成在全局位线上，均匀分离，并沿第一方向延伸。

    PHASE-CHANGE RANDOM ACCESS MEMORY AND METHOD OF SETTING BOOT BLOCK THEREIN
    6.
    发明申请
    PHASE-CHANGE RANDOM ACCESS MEMORY AND METHOD OF SETTING BOOT BLOCK THEREIN 有权
    相变随机访问存储器和设置引导块的方法

    公开(公告)号：US20090235036A1

    公开(公告)日：2009-09-17

    申请号：US12402006

    申请日：2009-03-11

    Applicant: Yu-hwan RO ,  Kwang-ho Kim ,  Kwang-jin Lee ,  Joon-yong Choi

    Inventor： Yu-hwan RO ,  Kwang-ho Kim ,  Kwang-jin Lee ,  Joon-yong Choi

    IPC: G06F12/16 ,  G06F12/00 ,  G06F12/02

    CPC classification number: G06F12/0238 ,  G06F12/0223 ,  Y02D10/13

    Abstract: A semiconductor memory device includes a memory cell array and the memory cell array includes: a plurality of memory blocks and at least one setting unit. The at least one setting unit stores a location and a size of a boot data storage region within the plurality of memory blocks that stores boot data. The at least one setting units may include a register for setting usage of each memory block as a boot block. The semiconductor device may be a phase-change memory.

    Abstract translation: 半导体存储器件包括存储单元阵列，存储单元阵列包括：多个存储块和至少一个设置单元。 所述至少一个设置单元将存储引导数据的多个存储块内的引导数据存储区域的位置和大小存储起来。 至少一个设置单元可以包括用于将每个存储器块的使用设置为引导块的寄存器。 半导体器件可以是相变存储器。

    Phase-changeable memory device and read method thereof
    8.
    发明申请
    Phase-changeable memory device and read method thereof 有权
    相变存储器件及其读取方法

    公开(公告)号：US20070133271A1

    公开(公告)日：2007-06-14

    申请号：US11605212

    申请日：2006-11-29

    Applicant: Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    Inventor： Woo-Yeong Cho ,  Byung-Gil Choi ,  Du-Eung Kim ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Yu-Hwan Ro

    IPC: G11C11/00

    CPC classification number: G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2213/72

    Abstract: Disclosed is a phase-changeable memory device and a related method of reading data. The memory device is comprised of memory cells, a high voltage circuit, a precharging circuit, a bias circuit, and a sense amplifier. Each memory cell includes a phase-changeable material and a diode connected to a bitline. The high voltage circuit provides a high voltage from a power source. The precharging circuit raises the bitline up to the high voltage after charging the bitline up to the power source voltage. The bias circuit supplies a read current to the bitline by means of the high voltage. The sense amplifier compares a voltage of the bitline with a reference voltage by means of the high voltage, and reads data from the memory cell. The memory device is able to reduce the burden on the high voltage circuit during the precharging operation, thus assuring a sufficient sensing margin during the sensing operation.

    Abstract translation: 公开了一种可变相存储器件和读取数据的相关方法。 存储器件包括存储器单元，高压电路，预充电电路，偏置电路和读出放大器。 每个存储单元包括相位可变材料和连接到位线的二极管。 高压电路从电源提供高电压。 预充电电路将位线充电至电源电压后，将位线升高至高电压。 偏置电路通过高电压向位线提供读取电流。 读出放大器通过高电压将位线的电压与参考电压进行比较，并从存储单元读取数据。 存储器件能够减少在预充电操作期间对高压电路的负担，从而在感测操作期间确保足够的感测余量。

    Non-volatile phase-change memory device and method of reading the same
    9.
    发明申请
    Non-volatile phase-change memory device and method of reading the same 有权
    非易失性相变存储器件及其读取方法

    公开(公告)号：US20070103972A1

    公开(公告)日：2007-05-10

    申请号：US11316017

    申请日：2005-12-23

    Applicant: Yu-Hwan Ro ,  Woo-Yeong Cho ,  Byung-Gil Choi

    Inventor： Yu-Hwan Ro ,  Woo-Yeong Cho ,  Byung-Gil Choi

    IPC: G11C11/00

    CPC classification number: G11C5/145 ,  G11C5/143 ,  G11C7/12 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2013/0057 ,  G11C2213/72

    Abstract: In one aspect, a non-volatile semiconductor memory device includes a phase phase-change memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of phase-change memory cells, where each the phase-change memory cells includes a phase-change resistive element and a diode connected in series between a word line and a bit line among the plurality of word lines and bit lines of the phase-change memory cell array. The memory device of this aspect further includes a sense node which is selectively connected to a bit line of the phase-change memory cell array, a boosting circuit which generates a boosted voltage which is greater than an internal power supply voltage, a pre-charge and biasing circuit which is driven by the boosted voltage to pre-charge and bias the sense node, and a sense amplifier connected to the sense node. The boosted voltage may be equal to or greater than a sum of the internal power supply voltage and a threshold voltage of the diode of each phase-change memory cell.

    Abstract translation: 一方面，一种非易失性半导体存储器件包括：相位相变存储单元阵列，包括多个字线，多个位线和多个相变存储器单元，其中每个相变存储器 单元包括在相变存储单元阵列的多个字线和位线之间串联连接在字线和位线之间的相变电阻元件和二极管。 该方面的存储装置还包括有选择地连接到相变存储单元阵列的位线的感测节点，产生大于内部电源电压的升压电压的升压电路，预充电 以及由升压电压驱动以对感测节点进行预充电和偏置的偏置电路，以及连接到感测节点的读出放大器。 升压电压可以等于或大于内部电源电压和每个相变存储单元的二极管的阈值电压之和。

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