公开(公告)号：US11894308B2

公开(公告)日：2024-02-06

申请号：US17109111

申请日：2020-12-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Ming Wang ,  Tien-Szu Chen ,  Wen-Chih Shen ,  Hsing-Wen Lee ,  Hsiang-Ming Feng

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L23/66 ,  H01L23/367 ,  H01P3/06 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/5383 ,  H01L23/66 ,  H01P3/06 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/48 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48225 ,  H01L2224/73253 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105

Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

公开(公告)号：US20140084475A1

公开(公告)日：2014-03-27

申请号：US13624548

申请日：2012-09-21

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Hsiang-Ming Feng ,  Yen-Hua Kuo

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/11462 ,  H01L2224/13018 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1401 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/007 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.

Abstract translation: 衬底包括第一介电层，第一电路图案，多个柱和第二电路图案。 第一电介质层具有相对的第一和第二电介质表面。 第一电路图案嵌入在第一电介质层中并且限定多个弯曲迹线表面。 每个支柱具有适于制造外部电连接的外表面和与相应的一个轨迹表面邻接的弯曲基底表面。 第二电路图案在第一电介质层的第二电介质表面上并且电连接到第一电路图案。

公开(公告)号：US08686568B2

公开(公告)日：2014-04-01

申请号：US13629397

申请日：2012-09-27

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Ming Wang ,  Hsiang-Ming Feng ,  Yen-Hua Kuo

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the barrier layer. The conductive pillars penetrate the core, the patterned metal layer, and the barrier layer, and contact the upper metal pattern. The conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer.

Abstract translation: 封装衬底包括芯，多个第一电路段和多个导电柱。 每个第一电路段具有设置在芯上的图案化金属层，设置在图案化金属层上的阻挡层和设置在阻挡层上的上部金属图案。 导电柱穿透芯，图案化金属层和阻挡层，并接触上部金属图案。 导电柱由可以选择性地去除而不影响阻挡层的材料形成。

公开(公告)号：US20140084480A1

公开(公告)日：2014-03-27

申请号：US13629397

申请日：2012-09-27

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Sheng-Ming Wang ,  Hsiang-Ming Feng ,  Yen-Hua Kuo

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The package substrate includes a core, a plurality of first circuit segments, and a plurality of conductive pillars. Each of the first circuit segments has a patterned metal layer disposed on the core, a barrier layer disposed on the patterned metal layer, and an upper metal pattern disposed on the barrier layer. The conductive pillars penetrate the core, the patterned metal layer, and the barrier layer, and contact the upper metal pattern. The conductive pillars are formed from a material that can be selectively removed without affecting the barrier layer.

Abstract translation: 封装衬底包括芯，多个第一电路段和多个导电柱。 每个第一电路段具有设置在芯上的图案化金属层，设置在图案化金属层上的阻挡层和设置在阻挡层上的上部金属图案。 导电柱穿透芯，图案化金属层和阻挡层，并接触上部金属图案。 导电柱由可以选择性地去除而不影响阻挡层的材料形成。

公开(公告)号：US20140308778A1

公开(公告)日：2014-10-16

申请号：US14313046

申请日：2014-06-24

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Hsiang-Ming Feng ,  Bing-Yun Cheng

IPC: H01L21/56

CPC classification number: H01L21/561 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/97 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00

Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices is attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.

Abstract translation: 制造半导体器件封装的方法的实施例包括散热器矩阵和衬底。 多个半导体器件附接到基板。 然后，在散热片基板和基板之间形成封装体，其中封装体封装半导体器件。 然后，形成多个第一切割槽，其中第一切割槽延伸穿过散热器矩阵并且部分地延伸到包装主体中。 然后，形成多个第二切割槽，其中第二切割槽延伸穿过基板并通过封装主体延伸到第一切割槽，从而将散热器矩阵和基板分离成多个单独的半导体器件封装。

公开(公告)号：US10854550B2

公开(公告)日：2020-12-01

申请号：US16109272

申请日：2018-08-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Ming Wang ,  Tien-Szu Chen ,  Wen-Chih Shen ,  Hsing-Wen Lee ,  Hsiang-Ming Feng

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48 ,  H01L23/66 ,  H01L23/367 ,  H01P3/06 ,  H01L21/683 ,  H01L23/00 ,  H01L25/065

Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.

公开(公告)号：US09054118B2

公开(公告)日：2015-06-09

申请号：US14313046

申请日：2014-06-24

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Hsiang-Ming Feng ,  Bing-Yun Cheng

IPC: H01L21/56 ,  H01L23/34 ,  H01L23/433 ,  H01L23/00

CPC classification number: H01L21/561 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/97 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00

Abstract: An embodiment of a method for making semiconductor device packages includes a heat sink matrix and a substrate. A plurality of semiconductor devices is attached to the substrate. Then, a package body is formed between the heat sink matrix and the substrate, wherein the package body encapsulates the semiconductor devices. Then, a plurality of first cutting slots is formed, wherein the first cutting slots extend through the heat sink matrix and partially extend into the package body. Then, a plurality of second cutting slots is formed, wherein the second cutting slots extend through the substrate and through the package body to the first cutting slot, thereby singulating the heat sink matrix and substrate into a plurality of individual semiconductor device packages.

Abstract translation: 制造半导体器件封装的方法的实施例包括散热器矩阵和衬底。 多个半导体器件附接到基板。 然后，在散热片基板和基板之间形成封装体，其中封装体封装半导体器件。 然后，形成多个第一切割槽，其中第一切割槽延伸穿过散热器矩阵并且部分地延伸到包装主体中。 然后，形成多个第二切割槽，其中第二切割槽延伸穿过基板并通过封装主体延伸到第一切割槽，从而将散热器矩阵和基板分离成多个单独的半导体器件封装。

公开(公告)号：US08866311B2

公开(公告)日：2014-10-21

申请号：US13624548

申请日：2012-09-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Hsiang-Ming Feng ,  Yen-Hua Kuo

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/11462 ,  H01L2224/13018 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1401 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/007 ,  H05K3/4007 ,  H05K2201/0367 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The substrate includes a first dielectric layer, a first circuit pattern, a plurality of pillars and a second circuit pattern. The first dielectric layer has opposing first and second dielectric surfaces. The first circuit pattern is embedded in the first dielectric layer and defines a plurality of curved trace surfaces. Each of the pillars has an exterior surface adapted for making external electrical connection and a curved base surface abutting a corresponding one of the trace surfaces. The second circuit pattern is on the second dielectric surface of the first dielectric layer and electrically connected to the first circuit pattern.

Abstract translation: 衬底包括第一介电层，第一电路图案，多个柱和第二电路图案。 第一电介质层具有相对的第一和第二电介质表面。 第一电路图案嵌入在第一电介质层中并且限定多个弯曲迹线表面。 每个支柱具有适于制造外部电连接的外表面和与相应的一个轨迹表面邻接的弯曲基底表面。 第二电路图案在第一电介质层的第二电介质表面上并且电连接到第一电路图案。