公开(公告)号：US20250113541A1

公开(公告)日：2025-04-03

申请号：US18291389

申请日：2022-08-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lizhong WANG ,  Guangcai YUAN ,  Ce NING ,  Hehe HU ,  Nianqi YAO ,  Dapeng XUE ,  Shuilang DONG ,  Liping LEI ,  Dongfang WANG ,  Zhengliang LI

IPC: H10D30/67 ,  H10D30/01

Abstract: An oxide thin film transistor, a preparation method thereof, and an electronic device are provided. The oxide thin film transistor includes a base substrate, a gate electrode and a metal oxide semiconductor layer, a gate insulation layer arranged between the metal oxide semiconductor layer and the gate electrode; the gate insulation layer includes a silicon oxide insulation layer and a silicon nitride layer, the silicon nitride layer adopts a single-layer structure or include a plurality of silicon nitride sublayers which are sequentially stacked, the silicon oxide insulation layer is between the silicon nitride layer and the metal oxide semiconductor layer; at least a part of a region in the silicon nitride layer satisfies that the percentage content of Si—H bonds in the sum of Si—N bonds, N—H bonds and Si—H bonds is not more than 7.

公开(公告)号：US20250098064A1

公开(公告)日：2025-03-20

申请号：US18552754

申请日：2022-10-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Nianqi YAO ,  Kun ZHAO ,  Ce NING ,  Zhengliang LI ,  Zhanfeng CAO ,  Ke WANG ,  Jiaxiang ZHANG ,  Qi QI ,  Hehe HU ,  Feifei LI ,  Jie HUANG ,  Jiayu HE

IPC: H05K1/02 ,  G02F1/1335 ,  G02F1/13357 ,  H05K1/11 ,  H05K3/28

Abstract: A circuit board includes a substrate, a first conductive layer, a first insulating layer and a second conductive layer. The first conductive layer includes a plurality of first conductive portions. The second conductive layer includes a plurality of second conductive portions. A second conductive portion passes through a first via hole in the first insulating layer to be in electrical contact with a first conductive portion. The first conductive layer and the second conductive layer each include at least one main conductive layer, which is capable of creating a first intermetallic compound with solder. At least one of the first conductive layer and the second conductive layer further includes a stop layer capable of creating a second intermetallic compound with the solder. A rate of a reaction between the stop layer and the solder is lower than a rate of a reaction between the main conductive layer and the solder.

公开(公告)号：US20250015092A1

公开(公告)日：2025-01-09

申请号：US18278413

申请日：2022-09-26

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lizhong WANG ,  Guangcai YUAN ,  Ce NING ,  Dongfang WANG ,  Liping LEI

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368

Abstract: Provided is an array substrate. The array substrate includes a display region and a non-display region located at a periphery of the display region, wherein the array substrate includes a substrate; a first transistor and a second transistor that are disposed on the substrate, wherein the first transistor is disposed in the display region, and the second transistor is disposed in the non-display region; and a data line and a pixel electrode that are disposed in the display region, wherein the data line is disposed on a side of the first active layer close to the substrate and is lapped with the first active layer, and the pixel electrode is disposed on a side of the first gate facing away from the substrate and is lapped with the first active layer.

公开(公告)号：US20240297256A1

公开(公告)日：2024-09-05

申请号：US17919387

申请日：2021-11-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Dongfang WANG ,  Lizhong WANG ,  Ce NING

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/6675 ,  H01L29/78633

Abstract: An array base plate includes a substrate; and a driving transistor and a switching transistor that are located on the substrate; the driving transistor includes a semiconductor layer; the switching transistor includes an active layer and a protecting layer, and the active layer includes two opposite main surfaces and a side surface that is located between outer contours of the two main surfaces; the protecting layer is located on a main surface of the active layer that is away from the substrate and covers the main surface and the side surface; the protecting layer and the semiconductor layer are arranged in a same layer, and a material of the protecting layer and a material of the semiconductor layer are a same metal-oxide-semiconductor material; and a carrier mobility of the protecting layer is less than a carrier mobility of the active layer.

公开(公告)号：US20240290890A1

公开(公告)日：2024-08-29

申请号：US18023766

申请日：2022-03-31

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Dongfang WANG ,  Lizhong WANG ,  Ce NING

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/41733

Abstract: A thin film transistor including a base substrate, and a drain, a source and an active layer on the base substrate, where the drain and the source are in different layers, respectively, and any two of an orthographic projection of the drain on the base substrate, an orthographic projection of the source on the base substrate and an orthographic projection of the active layer on the base substrate at least partially overlap each other.

公开(公告)号：US20240234532A1

公开(公告)日：2024-07-11

申请号：US17925222

申请日：2021-12-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Hehe HU ,  Dongfang WANG ,  Fengjuan LIU ,  Ce NING ,  Zhengliang LI ,  Jiayu HE ,  Yan QU ,  Kun ZHAO ,  Jie HUANG ,  Liping LEI ,  Yunsik IM ,  Shunhang ZHANG ,  Nianqi YAO ,  Feifei LI

IPC: H01L29/43 ,  H01L27/12 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/435 ,  H01L27/1214 ,  H01L29/41733 ,  H01L29/66742

Abstract: The present disclosure provides a TFT, a manufacturing method and a display substrate, and it relates to the field of TFT technology. The TFT includes: a base substrate; a gate electrode arranged on the base substrate; an active layer arranged at a side of the gate electrode away from the base substrate, an orthogonal projection of the active layer onto the base substrate overlapping with an orthogonal projection of the gate electrode onto the base substrate; and a source electrode and a drain electrode arranged at a side of the active layer away from the base substrate and coupled to the active layer. A resistance between the gate electrode and the drain electrode is greater than a resistance between the gate electrode and the source electrode. According to the present disclosure, it is able to increase a withstand voltage range of the TFT.

公开(公告)号：US20240212773A1

公开(公告)日：2024-06-27

申请号：US17909129

申请日：2021-10-25

Applicant: BOE Technology Group Co., Ltd.

Inventor： Fengjuan LIU ,  Ce NING ,  Wei LIU ,  Dini XIE ,  Yuhang LU

IPC: G11C19/28 ,  G09G3/20

CPC classification number: G11C19/28 ,  G09G3/2092 ,  G09G2300/0842 ,  G09G2310/0267 ,  G09G2310/0286

Abstract: The present disclosure provides a shift register unit, and driving method therefor, a gate drive circuit, and a display device, belonging to the field of display technologies. The shift register unit includes an input circuit, a compensation control circuit, and an output circuit. The input circuit can control a potential of a first node under control of an input signal provided by an input signal terminal and control a potential of a reference node under control of the input signal and an input control signal provided by an input control terminal. The compensation control circuit can adjust the potential of the first node based on the potential of the reference node under control of a first clock signal provided by a first clock signal terminal. In this way, the flexibility of controlling the first node is improved. Thus, the output circuit can flexibly output a drive signal to an output terminal coupled to a gate line under control of the first node.

公开(公告)号：US20240097042A1

公开(公告)日：2024-03-21

申请号：US17781773

申请日：2021-06-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lizhong WANG ,  Guangcai YUAN ,  Ce NING ,  Nianqi YAO ,  Hehe HU ,  Liping LEI ,  Dongfang WANG ,  Dapeng XUE ,  Shuilang DONG ,  Zhengliang LI

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742

Abstract: At least one embodiment of the present disclosure provides an oxide thin film transistor, a display device, and a preparation method of the oxide thin film transistor, and the oxide thin film transistor includes a base substrate; an oxide semiconductor layer provided on the base substrate, and an insulating layer provided on a side of the oxide semiconductor layer away from the base substrate; in which the insulating layer is made of oxide; the insulating layer includes a first insulating layer and a second insulating layer which are stacked; a density of the second insulating layer is greater than a density of the first insulating layer; and the second insulating layer is farther away from the base substrate than the first insulating layer.

公开(公告)号：US20240092628A1

公开(公告)日：2024-03-21

申请号：US18517694

申请日：2023-11-22

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaochen MA ,  Guangcai YUAN ,  Ce NING ,  Xin GU ,  Xiao ZHANG ,  Chao LI

IPC: B81B1/00 ,  B01L3/00 ,  B81C1/00

CPC classification number: B81B1/002 ,  B01L3/502715 ,  B81C1/00071 ,  B01L2300/0645 ,  B81B2201/05 ,  B81B2203/0338 ,  B81C2201/0111 ,  B81C2201/036

Abstract: A micro-nano channel structure, a method for manufacturing the micro-nano channel structure, a sensor, a method for manufacturing the sensor, and a microfluidic device are provided. The micro-nano channel structure includes: a base substrate; a base layer, on the base substrate and including a plurality of protrusions; a channel wall layer, on a side of the plurality of the protrusions away from the base substrate, the channel wall layer has a micro-nano channel; a recessed portion is provided between adjacent protrusions of the plurality of the protrusions, an orthographic projection of the micro-nano channel on the base substrate is located within an orthographic projection of the recessed portion on the base substrate. The micro-nano channels have a high resolution or an ultra-high resolution, and have different sizes and shapes.

公开(公告)号：US20230036385A1

公开(公告)日：2023-02-02

申请号：US17772689

申请日：2021-06-24

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiayu HE ,  Ce NING ,  Zhengliang LI ,  Hehe HU ,  Jie HUANG ,  Nianqi YAO ,  Kun ZHAO ,  Xue LIU ,  Zhi WANG ,  Feng GUAN

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: The disclosure provides a thin-film transistor, a manufacturing method thereof, an array substrate and a display panel, and belongs to the technical field of thin-film transistor devices. The thin-film transistor includes a base substrate, an active layer on the base substrate including a plurality of semiconductor nanowires, and a plurality of guiding projections on the base substrate which extend along a first direction and are arranged at intervals and each of which includes two side walls extending along the first direction, and the semiconductor nanowire extends along a side wall of the guiding projection. In the thin-film transistor, since the semiconductor nanowires are used as the active layer, mobility and concentration of carriers in the thin-film transistor can be effectively increased and therefore performance of the thin-film transistor can be improved. A length of the semiconductor nanowire is not limited, and a size of the thin-film transistor is not limited.