公开(公告)号：US07259984B2

公开(公告)日：2007-08-21

申请号：US10718662

申请日：2003-11-24

申请人： Edwin C. Kan ,  Zengtao Liu ,  Chungho Lee

发明人： Edwin C. Kan ,  Zengtao Liu ,  Chungho Lee

IPC分类号： G11C11/34

CPC分类号： H01L21/28273 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0491 ,  G11C2216/06

摘要： Metal nanocrystal memories are fabricated to include higher density states, stronger coupling with the channel, and better size scalability, than has been available with semiconductor nanocrystal devices. A self-assembled nanocrystal formation process by rapid thermal annealing of ultra thin metal film deposited on top of gate oxide is integrated with NMOSFET to fabricate such devices. Devices with Au, Ag, and Pt nanocrystals working in the F-N tunneling regime, with hot-carrier injection as the programming mechanism, demonstrate retention times up to 106s, and provide 2-bit-per-cell storage capability.

摘要翻译： 金属纳米晶体存储器被制造成包括比半导体纳米晶体器件可用的更高密度状态，更强的与沟道的耦合以及更好的尺寸可扩展性。 通过沉积在栅极氧化物顶部的超薄金属膜的快速热退火的自组装纳米晶体形成工艺与NMOSFET集成以制造这种器件。 具有在FN隧穿状态下工作的Au，Ag和Pt纳米晶体的器件以热载流子注入作为编程机制，证明保留时间高达10 6，并提供2位/ 细胞储存能力。

公开(公告)号：US06646302B2

公开(公告)日：2003-11-11

申请号：US09911378

申请日：2001-07-25

申请人： Edwin C. Kan ,  Zengtao Liu ,  Venkatasubraman Narayanan

发明人： Edwin C. Kan ,  Zengtao Liu ,  Venkatasubraman Narayanan

IPC分类号： H01L29788

CPC分类号： B82Y10/00 ,  H01L21/2855 ,  H01L29/42332

摘要： Low resistance metal/semiconductor and metal/insulator contacts incorporate metal nanocrystals embedded in another metal having a different work function. The contacts are fabricated by placing a wetting layer of a first metal on a substrate, which may be a semiconductor or an insulator and then heating to form nanocrystals on the semiconductor or insulator surface. A second metal having a different work function than the first is then deposited on the surface so that the nanocrystals are embedded in the second material.

公开(公告)号：US06743709B2

公开(公告)日：2004-06-01

申请号：US10210993

申请日：2002-08-05

申请人： Edwin C. Kan ,  Zengtao Liu ,  Venkatasubraman Narayanan

发明人： Edwin C. Kan ,  Zengtao Liu ,  Venkatasubraman Narayanan

IPC分类号： H01L214763

CPC分类号： B82Y10/00 ,  H01L21/2855 ,  H01L29/42332

摘要： Low resistance metal/semiconductor and metal/insulator contacts incorporate metal nanocrystals embedded in another metal having a different work function. The contacts are fabricated by placing a wetting layer of a first metal on a substrate, which may be a semiconductor or an insulator and then heating to form nanocrystals on the semiconductor or insulator surface. A second metal having a different work function than the first is then deposited on the surface so that the nanocrystals are embedded in the second material.

摘要翻译： 低电阻金属/半导体和金属/绝缘体触点并入嵌入另一种具有不同功函数的金属中的金属纳米晶体。 通过将第一金属的润湿层放置在可以是半导体或绝缘体的衬底上，然后加热以在半导体或绝缘体表面上形成纳米晶体来制造触点。 然后将具有与第一种功能不同的功函的第二金属沉积在表面上，使得纳米晶体嵌入第二材料中。

公开(公告)号：US08508999B2

公开(公告)日：2013-08-13

申请号：US13451656

申请日：2012-04-20

申请人： Zengtao Liu ,  Graham Wolstenholme

发明人： Zengtao Liu ,  Graham Wolstenholme

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11582

摘要： A vertical NAND structure includes one or more mid-string devices having at least two functional modes. In the first mode, the one or more mid-string devices couple the bodies of stacks of NAND memory cells to the substrate for erase operations. In the second mode, the one or more mid-string devices couple the body of a first stack of NAND memory cells to a body of a second stack of memory NAND memory cells, allowing the two stacks operate as a single NAND string for read and programming operations.

摘要翻译： 垂直NAND结构包括具有至少两个功能模式的一个或多个中串式装置。 在第一模式中，一个或多个中串式装置将NAND存储器单元堆叠的主体耦合到衬底以进行擦除操作。 在第二模式中，一个或多个中串装置将第一堆NAND存储器单元的主体耦合到第二堆存储器NAND存储器单元的主体，允许两个堆作为单个NAND串用于读取和 编程操作。

公开(公告)号：US20120012921A1

公开(公告)日：2012-01-19

申请号：US12836853

申请日：2010-07-15

申请人： Zengtao Liu

发明人： Zengtao Liu

IPC分类号： H01L27/088 ,  H01L21/8239

CPC分类号： H01L27/088 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of the respective strings in series. For some embodiments, two dielectric pillars may be formed from a dielectric formed in a single opening, where each of the dielectric pillars has a pair of memory-cell strings adjacent thereto and where at least one memory cell of one of the strings on one of the pillars and at least one memory cell of one of the strings on the other pillar are commonly coupled to an access line.

公开(公告)号：US20060216922A1

公开(公告)日：2006-09-28

申请号：US11407429

申请日：2006-04-20

申请人： Luan Tran ,  John Lee ,  Zengtao Liu ,  Eric Freeman ,  Russell Nielsen

发明人： Luan Tran ,  John Lee ,  Zengtao Liu ,  Eric Freeman ,  Russell Nielsen

IPC分类号： H01L21/4763 ,  H01L21/302

CPC分类号： H01L21/0334 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/544 ,  H01L27/1052 ,  H01L2924/0002 ,  Y10S438/947 ,  H01L2924/00

摘要： A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

公开(公告)号：US08559231B2

公开(公告)日：2013-10-15

申请号：US13043005

申请日：2011-03-08

申请人： Akira Goda ,  Zengtao Liu

发明人： Akira Goda ,  Zengtao Liu

IPC分类号： G11C16/06

CPC分类号： G11C16/10 ,  G11C5/02 ,  G11C5/025 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/28

摘要： One method for sensing includes changing a sense condition of a particular layer responsive to a programming rate of that particular layer (e.g., relative to other layers). In one embodiment, the target threshold voltage range can be shifted lower for a slower programming layer. This might be accomplished by biasing the bit lines of slower programming layers with higher bit line voltages as compared to bit line voltages of faster programming layers.

摘要翻译： 用于感测的一种方法包括响应于该特定层的编程速率（例如，相对于其它层）改变特定层的感测条件。 在一个实施例中，对于较慢的编程层，目标阈值电压范围可以更低。 与较快编程层的位线电压相比，可以通过将较慢编程层的位线与较高位线电压相比较来实现。

公开(公告)号：US20130003435A1

公开(公告)日：2013-01-03

申请号：US13607681

申请日：2012-09-08

申请人： Zengtao Liu

发明人： Zengtao Liu

IPC分类号： G11C5/06

CPC分类号： G01R33/58 ,  G01R33/1284 ,  G01R33/24 ,  G11C5/025 ,  G11C5/063 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/003 ,  G11C2213/18 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144

摘要： Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.

公开(公告)号：US20120230116A1

公开(公告)日：2012-09-13

申请号：US13043005

申请日：2011-03-08

申请人： Akira Goda ,  Zengtao Liu

发明人： Akira Goda ,  Zengtao Liu

IPC分类号： G11C16/06 ,  G11C16/26

CPC分类号： G11C16/10 ,  G11C5/02 ,  G11C5/025 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/28

摘要： Methods for sensing and memory devices are disclosed. One such method for sensing includes changing a sense condition of a particular layer responsive to a programming rate of that particular layer (e.g., relative to other layers).

摘要翻译： 公开了用于感测和存储器件的方法。 用于感测的一种这样的方法包括响应于该特定层的编程速率（例如，相对于其他层）改变特定层的感测条件。

公开(公告)号：US08237213B2

公开(公告)日：2012-08-07

申请号：US12836853

申请日：2010-07-15

申请人： Zengtao Liu

发明人： Zengtao Liu

IPC分类号： H01L29/792 ,  H01L21/8239

CPC分类号： H01L27/088 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of the respective strings in series. For some embodiments, two dielectric pillars may be formed from a dielectric formed in a single opening, where each of the dielectric pillars has a pair of memory-cell strings adjacent thereto and where at least one memory cell of one of the strings on one of the pillars and at least one memory cell of one of the strings on the other pillar are commonly coupled to an access line.

摘要翻译： 公开了其阵列及其形成方法。 一个这样的存储器阵列具有与分离的基本上垂直的相邻半导体结构相邻的存储单元串，其中分离的半导体结构将各个串的存储单元串联耦合。 对于一些实施例，两个介电柱可以由在单个开口中形成的电介质形成，其中每个介电柱具有与其相邻的一对存储单元串，并且其中一个串中的至少一个存储单元位于 支柱和另一个支柱上的串中的一个的至少一个存储单元通常耦合到接入线。