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公开(公告)号：US20050082624A1
公开(公告)日：2005-04-21
申请号：US10689222
申请日：2003-10-20
IPC分类号： H01L21/28 , H01L21/316 , H01L29/51 , H01L29/94
CPC分类号： H01L21/28194 , H01L21/02112 , H01L21/02271 , H01L21/0228 , H01L21/28264 , H01L21/31604 , H01L29/517 , H01L29/518
摘要： A structure, and method of fabrication, for high performance semiconductor field effect devices is disclosed. These devices are having a gate dielectric containing a germanate material. In representative embodiments the gate dielectric is essentially a layer of a germanate material. The chemical composition of such materials is MezGexOy, where Me stands for a metal with high ion polarizability, and x, y, and z are non-zero integers. Such a gate dielectric is advantageous, from the point of view of dielectric constant, barrier height, carrier mobility, thermal stability, and interface stability.
摘要翻译： 公开了一种用于高性能半导体场效应器件的结构和制造方法。 这些器件具有含有锗酸盐材料的栅极电介质。 在代表性的实施例中，栅极电介质基本上是锗酸盐材料层。 这种材料的化学成分是Me z O x O x O y，其中Me代表具有高离子极化率的金属，x，y ，z是非零整数。 从介电常数，势垒高度，载流子迁移率，热稳定性和界面稳定性的观点来看，这种栅极电介质是有利的。
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公开(公告)号：US20060202279A1
公开(公告)日：2006-09-14
申请号：US11413532
申请日：2006-04-29
CPC分类号： H01L21/28202 , H01L21/02247 , H01L21/02326 , H01L21/02337 , H01L21/0234 , H01L21/28255 , H01L21/3143 , H01L21/31658 , H01L21/318 , H01L29/518 , Y10S438/906 , Y10S438/933
摘要： A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.
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公开(公告)号：US07078300B2
公开(公告)日：2006-07-18
申请号：US10672631
申请日：2003-09-27
IPC分类号： H01L21/336
CPC分类号： H01L21/28202 , H01L21/02247 , H01L21/02326 , H01L21/02337 , H01L21/0234 , H01L21/28255 , H01L21/3143 , H01L21/31658 , H01L21/318 , H01L29/518 , Y10S438/906 , Y10S438/933
摘要： A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.
摘要翻译： 公开了用作栅极电介质的Ge基材料上产生6nm以下等效氧化物厚度薄的锗氮氧化物层的方法。 该方法涉及两步法。 首先，在Ge基材料的表层中加入氮。 其次，氮掺入之后是氧化步骤。 该方法为基于Ge的场效应器件（例如MOS晶体管）的高质量栅极电介质产生优异的厚度控制。 还公开了具有薄氮氧化锗栅电介质的器件的结构和用这种器件制造的处理器。
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公开(公告)号：US20050070122A1
公开(公告)日：2005-03-31
申请号：US10672631
申请日：2003-09-27
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L21/318 , H01L29/51 , H01L21/469
CPC分类号： H01L21/28202 , H01L21/02247 , H01L21/02326 , H01L21/02337 , H01L21/0234 , H01L21/28255 , H01L21/3143 , H01L21/31658 , H01L21/318 , H01L29/518 , Y10S438/906 , Y10S438/933
摘要： A method for producing thin, below 6 nm of equivalent oxide thickness, germanium oxynitride layer on Ge-based materials for use as gate dielectric is disclosed. The method involves a two step process. First, nitrogen is incorporated in a surface layer of the Ge-based material. Second, the nitrogen incorporation is followed by an oxidation step. The method yields excellent thickness control of high quality gate dielectrics for Ge-based field effect devices, such as MOS transistors. Structures of devices having the thin germanium oxynitride gate dielectric and processors made with such devices are disclosed, as well.
摘要翻译： 公开了用作栅极电介质的Ge基材料上产生6nm以下等效氧化物厚度薄的锗氮氧化物层的方法。 该方法涉及两步法。 首先，在Ge基材料的表层中加入氮。 其次，氮掺入之后是氧化步骤。 该方法为基于Ge的场效应器件（例如MOS晶体管）的高质量栅极电介质产生优异的厚度控制。 还公开了具有薄氮氧化锗栅电介质的器件的结构和用这种器件制造的处理器。
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公开(公告)号：US08558313B2
公开(公告)日：2013-10-15
申请号：US13425681
申请日：2012-03-21
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/088
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译： 提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度， 与SOI FET的掩埋绝缘层基本共面。 在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成体FET。 邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。
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6.发明授权Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby 有权自对准金属与Ge形成的基板和由此形成的结构形成接触公开(公告)号：US08154130B2
公开(公告)日：2012-04-10
申请号：US12107992
申请日：2008-04-23
申请人： Cyril Cabral, Jr. , Roy A. Carruthers , Christophe Detavernier , Simon Gaudet , Christian Lavoie , Huiling Shang
发明人： Cyril Cabral, Jr. , Roy A. Carruthers , Christophe Detavernier , Simon Gaudet , Christian Lavoie , Huiling Shang
IPC分类号： H01L29/40
CPC分类号： H01L21/28525 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.
摘要翻译： 提供了一种形成锗硅化物的方法，该方法与由纯金属形成的常规硅化物接触相比更能抵抗蚀刻的含Ge层顶部接触。 本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。 在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。 在暴露的区域中，含Ge衬底与含Si金属层接触。 然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。 在一些实施方案中，附加的退火步骤可以跟随去除步骤。 本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。
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7.发明申请公开(公告)号：US20110318897A1
公开(公告)日：2011-12-29
申请号：US12823168
申请日：2010-06-25
申请人： Huiling Shang , Ying Li , Henry K. Utomo
发明人： Huiling Shang , Ying Li , Henry K. Utomo
IPC分类号： H01L21/02
CPC分类号： H01L28/20 , H01L21/76229 , H01L27/0629
摘要： Forming a polysilicon embedded resistor within the shallow trench isolations separating the active area of two adjacent devices, minimizing the electrical interaction between two devices and reducing the capacitive coupling or leakage therebetween. The precision polysilicon resistor is formed independently from the formation of gate electrodes by creating a recess region within the STI region when the polysilicon resistor is embedded within the STI recess region. The polysilicon resistor is decoupled from the gate electrode, making it immune to gate electrode related processes. The method forms the polysilicon resistor following the formation of STIs but before the formation of the p-well and n-well implants. In another embodiment the resistor is formed following the formation of the STIs but after the formation of the well implants.
摘要翻译： 在分离两个相邻器件的有源区域的浅沟槽隔离件之间形成多晶硅嵌入式电阻器，最小化两个器件之间的电气相互作用，并减少它们之间的电容耦合或泄漏。 当多晶硅电阻器嵌入STI凹陷区域内时，通过在STI区域内形成凹陷区域，独立于形成栅电极而形成精密多晶硅电阻器。 多晶硅电阻器与栅极电极分离，使其免受与栅电极相关的工艺的影响。 该方法在形成STI之后但在形成p阱和n阱注入之前形成多晶硅电阻器。 在另一个实施例中，在形成STI之后但在形成井注入之后形成电阻器。
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公开(公告)号：US20090212366A1
公开(公告)日：2009-08-27
申请号：US12434233
申请日：2009-05-01
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795
摘要： A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. In accordance with the present invention, the inventive structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together.
摘要翻译： 提供了一种具有融合在一起而没有源极/漏极接触焊盘或局部互连的多个FIN的具有FINFET的结构。 根据本发明，本发明的结构包括在衬底的表面上方延伸的多个半导电体（即，FIN）。 常见的图案化栅极堆叠围绕多个半导体本体，并且含氮化物的间隔物位于公共图案化栅叠层的侧壁上。 使用外延半导体层将每个半导电体合并在一起。
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公开(公告)号：US08969969B2
公开(公告)日：2015-03-03
申请号：US12727312
申请日：2010-03-19
申请人： Victor W. C. Chan , Narasimhulu Kanike , Huiling Shang , Varadarajan Vidya , Jun Yuan , Roger Allen Booth, Jr.
发明人： Victor W. C. Chan , Narasimhulu Kanike , Huiling Shang , Varadarajan Vidya , Jun Yuan , Roger Allen Booth, Jr.
IPC分类号： H01L27/092 , H01L21/8234 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823412
摘要： Transistors exhibiting different electrical characteristics such as different switching threshold voltage or different leakage characteristics are formed on the same chip or wafer by selectively removing a film or layer which can serve as an out-diffusion sink for an impurity region such as a halo implant and out-diffusing an impurity such as boron into the out-diffusion sink, leaving the impurity region substantially intact where the out-diffusion sink has been removed. In forming CMOS integrated circuits, such a process allows substantially optimal design for both low-leakage and low threshold transistors and allows a mask and additional associated processes to be eliminated, particularly where a tensile film is employed to increase electron mobility since the tensile film can be removed from selected NMOS transistors concurrently with removal of the tensile film from PMOS transistors.
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公开(公告)号：US08080838B2
公开(公告)日：2011-12-20
申请号：US12434233
申请日：2009-05-01
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795
摘要： A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. The structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together.
摘要翻译： 提供了一种具有融合在一起而没有源极/漏极接触焊盘或局部互连的多个FIN的具有FINFET的结构。 该结构包括在衬底的表面上方延伸的多个半导电体（即，FIN）。 常见的图案化栅极堆叠围绕多个半导体本体，并且含氮化物的间隔物位于公共图案化栅叠层的侧壁上。 使用外延半导体层将每个半导电体合并在一起。
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