公开(公告)号：US06359307B1

公开(公告)日：2002-03-19

申请号：US09493436

申请日：2000-01-29

申请人： Fei Wang ,  Hiroyuki Kinoshita ,  Kashmir Sahota ,  Yu Sun ,  Wenge Yang

发明人： Fei Wang ,  Hiroyuki Kinoshita ,  Kashmir Sahota ,  Yu Sun ,  Wenge Yang

IPC分类号： H01L2976

CPC分类号： H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y02P80/30 ,  H01L2924/00

摘要： The present invention further provides a method for forming self-aligned contacts using a dual damascene techniques that reduces the number of process steps and results in a reduction in cycle time, cost and yield loss. In a preferred embodiment, a method for forming a contact and a channel in a dielectric layer over a region on a semiconductor substrate is provided. The contact is self-aligned. The contact and channel are formed by (1) forming a contact opening in the dielectric layer, (2) forming a channel opening in the dielectric layer, wherein the channel opening encompasses the contact opening, (3) extending the contact opening to expose a portion of the region on the semiconductor substrate; and (4) filling the contact opening and the channel opening with a conductive material to form a contact and a channel, respectively.

摘要翻译： 本发明还提供了一种使用双镶嵌技术形成自对准接触的方法，其减少了工艺步骤的数量并导致了循环时间，成本和屈服损失的降低。 在优选实施例中，提供了在半导体衬底上的区域上形成电介质层中的接触和沟道的方法。 联系人自行对齐。 接触和通道由（1）在电介质层中形成接触开口形成，（2）在电介质层中形成通道开口，其中通道开口包围接触开口，（3）延伸接触开口以露出 所述半导体衬底上的所述区域的部分; 和（4）分别用导电材料填充接触开口和通道开口以形成接触和通道。

公开(公告)号：US06376389B1

公开(公告)日：2002-04-23

申请号：US09588117

申请日：2000-05-31

申请人： Ramkumar Subramanian ,  Minh Van Ngo ,  Kashmir Sahota ,  Yongzhong Hu ,  Hiroyuki Kinoshita ,  Fei Wang ,  Wenge Yang

发明人： Ramkumar Subramanian ,  Minh Van Ngo ,  Kashmir Sahota ,  Yongzhong Hu ,  Hiroyuki Kinoshita ,  Fei Wang ,  Wenge Yang

IPC分类号： H01L2100

CPC分类号： H01L21/76802 ,  H01L21/76895 ,  H01L23/522 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for manufacturing a semiconductor device without the use of an anti-reflective coating. In one embodiment, electrical devices are formed on a semiconductor substrate. A material with a low dielectric constant such as an oxide is then deposited. The low dielectric layer is then covered with photoresist and photolithographically processed and subsequently developed. The low dielectric layer is then etched using the pattern formed on the photoresist and the photoresist is later removed. Because this process works in any similar circumstances, good examples of its application are the formation of both contacts and local interconnects.

摘要翻译： 本发明提供一种不使用抗反射涂层的半导体器件的制造方法。 在一个实施例中，电子器件形成在半导体衬底上。 然后沉积具有低介电常数的材料，例如氧化物。 然后用光致抗蚀剂覆盖低介电层，并进行光刻处理并随后显影。 然后使用形成在光致抗蚀剂上的图案蚀刻低介电层，随后去除光致抗蚀剂。 因为这个过程在任何类似的情况下都可以工作，它的应用的很好的例子是形成两个触点和局部互连。

公开(公告)号：US06348406B1

公开(公告)日：2002-02-19

申请号：US09586264

申请日：2000-05-31

申请人： Ramkumar Subramanian ,  Minh Van Ngo ,  Kashmir Sahota ,  Yongzhong Hu ,  Hiroyuki Kinoshita ,  Fei Wang ,  Wenge Yang

发明人： Ramkumar Subramanian ,  Minh Van Ngo ,  Kashmir Sahota ,  Yongzhong Hu ,  Hiroyuki Kinoshita ,  Fei Wang ,  Wenge Yang

IPC分类号： H01L214763

CPC分类号： H01L27/11521 ,  H01L21/31144

摘要： The present invention provides a method for manufacturing a semiconductor device with an anti-reflective coating (ARC) that does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. A dielectric layer is then deposited over the electrical devices and the semiconductor substrate, upon which an optically transparent ARC layer of low dielectric constant is then deposited. Photoresist is then deposited on top of the ARC layer and is then photolithographically processed and subsequently developed. The dielectric layer is then etched down to the semiconductor substrate to form contacts or local interconnects. The ARC layer can subsequently be used as a hard mask and does not require removal.

摘要翻译： 本发明提供一种制造具有不需要去除的抗反射涂层（ARC）的半导体器件的方法。 在一个实施例中，电子器件形成在半导体衬底上。 然后将电介质层沉积在电气器件和半导体衬底上，然后沉积出具有低介电常数的光学透明ARC层。 然后将光致抗蚀剂沉积在ARC层的顶部上，然后光刻加工并随后显影。 然后将电介质层向下蚀刻到半导体衬底以形成接触或局部互连。 ARC层可以随后用作硬掩模，并且不需要去除。

公开(公告)号：US20060223278A1

公开(公告)日：2006-10-05

申请号：US11099339

申请日：2005-04-04

申请人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun ,  Krishnashree Achuthan ,  Christopher Raeder ,  Christopher Foster ,  Harpreet Sachar ,  Kashmir Sahota

发明人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun ,  Krishnashree Achuthan ,  Christopher Raeder ,  Christopher Foster ,  Harpreet Sachar ,  Kashmir Sahota

IPC分类号： H01L21/76

CPC分类号： H01L27/105 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11568

摘要： A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.

摘要翻译： 公开了一种用于在半导体晶片中定义多晶硅层的方法。 使用非临界掩模在聚-1沉积之前将外围的场氧化物凹入等于最终聚-1厚度的量。 使用互补的非关键掩模来允许芯的CMP将浅层隔离沟的核心氧化物台面的顶部暴露出来。

公开(公告)号：US6136649A

公开(公告)日：2000-10-24

申请号：US416389

申请日：1999-10-12

申请人： Angela T. Hui ,  Wenge Yang ,  Kashmir Sahota ,  Mark T. Ramsbey ,  Suzette K. Pangrle ,  Minh Van Ngo

发明人： Angela T. Hui ,  Wenge Yang ,  Kashmir Sahota ,  Mark T. Ramsbey ,  Suzette K. Pangrle ,  Minh Van Ngo

IPC分类号： H01L21/311 ,  H01L21/336 ,  H01L21/8247

CPC分类号： H01L27/11521 ,  H01L21/31116 ,  H01L29/66825

摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane (CH.sub.3 F)/oxygen (O.sub.2) etch chemistry is used to selectively remove the ARC layer. The CH.sub.3 F/O.sub.2 etch chemistry etches the ARC layer at a rate which is significantly faster than the etch rates of the dielectric layer or the tungsten contacts.

摘要翻译： 本发明提供一种用于在基板表面上从电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨触点。 在一个实施方案中，使用氟甲烷（CH 3 F）/氧（O 2）蚀刻化学物质来选择性地除去ARC层。 CH3F / O2蚀刻化学蚀刻ARC层的速度明显快于介电层或钨触点的蚀刻速率。

公开(公告)号：US06291296B1

公开(公告)日：2001-09-18

申请号：US09416382

申请日：1999-10-12

申请人： Angela T. Hui ,  Wenge Yang ,  Kashmir Sahota ,  Mark T. Ramsbey ,  Suzette K. Pangrle ,  Minh Van Ngo

发明人： Angela T. Hui ,  Wenge Yang ,  Kashmir Sahota ,  Mark T. Ramsbey ,  Suzette K. Pangrle ,  Minh Van Ngo

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115 ,  Y10S438/951

摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of an dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane (CH3F)/oxygen (O2) etch chemistry is used to selectively remove the ARC layer without scratching and/or degradation of the dielectric layer, source/drain regions formed over the substrate, and a silicide layer formed atop stacked gate structures. The CH3F/O2 etch chemistry etches the ARC layer at a rate which is significantly faster than the etch rates of the dielectric layer, the source/drain regions and the silicide layer. In addition, by removing the ARC layer prior to the formation of tungsten contacts by filling of contact openings formed in the dielectric layer with tungsten, potential scratching of tungsten contacts due to ARC layer removal is eliminated.

摘要翻译： 本发明提供了一种从基板表面上的电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨触点。 在一个实施方案中，使用氟甲烷（CH 3 F）/氧（O 2）蚀刻化学物质来选择性地除去ARC层，而不会在电介质层，形成在衬底上的源极/漏极区域的划伤和/或降解，以及形成在顶部的硅化物层 堆叠门结构。 CH3F / O2蚀刻化学以比介电层，源/漏区和硅化物层的蚀刻速率明显更快的速率蚀刻ARC层。 此外，通过在形成钨触点之前，通过用钨填充形成在电介质层中的接触开口来去除ARC层，消除了由于ARC层去除引起的钨触点的潜在划痕。

公开(公告)号：US06518185B1

公开(公告)日：2003-02-11

申请号：US10127521

申请日：2002-04-22

申请人： Pin-Chin Connie Wang ,  Fei Wang ,  Kashmir Sahota ,  Steven Avanzino ,  Amit Marathe ,  Matthew Buynoski ,  Ercan Adem ,  Christy Woo

发明人： Pin-Chin Connie Wang ,  Fei Wang ,  Kashmir Sahota ,  Steven Avanzino ,  Amit Marathe ,  Matthew Buynoski ,  Ercan Adem ,  Christy Woo

IPC分类号： H01L2144

CPC分类号： H01L21/76877

摘要： In the present method of fabricating a semiconductor device, openings of different configurations (for example, different aspect ratios) are provided in a dielectric layer. Substantially undoped copper is deposited over the dielectric layer, filling the openings and extending above the dielectric layer, the different configurations of the openings providing an upper surface of the substantially undoped copper that is generally non-planar. A portion of the substantially undoped copper is removed to provide a substantially planar upper surface thereof, and a layer of doped copper is deposited on the upper surface of the substantially undoped copper. An anneal step is undertaken to difffuse the doping element into the copper in the openings.

摘要翻译： 在本发明的半导体装置的制造方法中，在介质层中设置不同结构（例如不同的纵横比）的开口。 基本上未掺杂的铜沉积在电介质层上，填充开口并在电介质层上方延伸，开口的不同构型提供通常为非平面的基本未掺杂的铜的上表面。 去除基本上未掺杂的铜的一部分以提供其基本平坦的上表面，并且在基本未掺杂的铜的上表面上沉积掺杂的铜层。 进行退火步骤以将掺杂元素扩散到开口中的铜中。

公开(公告)号：US06004862A

公开(公告)日：1999-12-21

申请号：US8320

申请日：1998-01-20

申请人： Unsoon Kim ,  Hung-Sheng Chen ,  Kashmir Sahota ,  Yu Sun

发明人： Unsoon Kim ,  Hung-Sheng Chen ,  Kashmir Sahota ,  Yu Sun

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76202 ,  H01L21/76224

摘要： A process for forming a semiconductor integrated circuit with a core area densely populated with active devices and with a periphery area less densely populated with active devices as compared to the core area, comprising the steps of: forming a first layer of first insulator material above a semiconductor substrate having a core area and a periphery area, wherein the first insulator material constitutes a polish stop for polishing processes and also as an oxidation barrier; patterning the first layer of first insulator material to expose first portions of the semiconductor substrate substantially only in the core area while using the first insulator material to substantially mask the periphery area; forming a plurality of trenches into the exposed first portions of semiconductor substrate in the core area; filling the plurality of trenches with an insulator; polishing down to the first layer of first insulator material; removing the first layer of first insulator material; forming a second layer of first insulator material over the core and periphery areas; forming openings down into the second layer of first insulator material to expose second portions of the semiconductor substrate substantially only in the periphery area while using the second layer to substantially mask the core area; and forming an isolation region in the exposed second portions of the semiconductor substrate.

摘要翻译： 一种用于形成半导体集成电路的方法，所述半导体集成电路具有密集地填充有有源器件的核心区域，并且与所述核心区域相比具有较少密集地填充有源器件的外围区域，包括以下步骤：在第一绝缘体材料的上方形成第一层 具有芯区域和周边区域的半导体衬底，其中所述第一绝缘体材料构成用于抛光工艺的抛光止挡件以及氧化屏障; 图案化第一绝缘体材料层，以在使用第一绝缘体材料基本上遮蔽周边区域的同时，在半导体衬底的基本上仅在芯部区域露出第一部分; 在芯区域中的半导体衬底的暴露的第一部分中形成多个沟槽; 用绝缘体填充多个沟槽; 抛光到第一绝缘体材料层; 去除第一绝缘体材料的第一层; 在所述芯和外围区域上形成第二绝缘体材料层; 将第一绝缘体材料的第二层向下形成开口，以便在使用第二层基本上掩蔽核心区域时，基本上只在周边区域露出半导体衬底的第二部分; 以及在半导体衬底的暴露的第二部分中形成隔离区。

公开(公告)号：US06133619A

公开(公告)日：2000-10-17

申请号：US144521

申请日：1998-08-31

申请人： Kashmir Sahota ,  Richard J. Huang ,  David Matsumoto ,  Mark T. Ramsbey ,  Yu Sun ,  Judith Quan Rizzuto

发明人： Kashmir Sahota ,  Richard J. Huang ,  David Matsumoto ,  Mark T. Ramsbey ,  Yu Sun ,  Judith Quan Rizzuto

IPC分类号： H01L21/312 ,  H01L21/314 ,  H01L21/768 ,  H01L51/00

CPC分类号： H01L21/76801 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/3124 ,  H01L21/3145

摘要： Outgassing from a dielectric gap fill layer, e.g., a low dielectric constant material such as HSQ, and attendant deformation or delamination of a barrier dielectric layer on an overlying patterned conductive layer during subsequent thermal processing are avoided or significantly reduced by controlling the thickness of the dielectric cap layer on the dielectric gap fill layer. Embodiments include depositing a conformal SiON barrier on a first conductive pattern, depositing a HSQ gap fill layer on the conformal SiON barrier layer, depositing a silicon oxide cap layer and planarizing such that the thickness of the planarized silicon cap layer is at least 2500 .ANG., thereby avoiding deformation and/or delamination of a conformal SiON barrier layer on an overlying patterned conductive layer during subsequent thermal processing.

摘要翻译： 从介电间隙填充层，例如低介电常数材料（例如HSQ）以及随后的热处理过程中覆盖的图案化导电层上的阻挡介电层的伴随变形或分层的脱气被避免或显着减少，通过控制 电介质间隙填充层上的介电覆盖层。 实施例包括在第一导电图案上沉积保形SiON阻挡层，在保形SiON阻挡层上沉积HSQ间隙填充层，沉积氧化硅覆盖层并进行平坦化，使得平坦化硅覆盖层的厚度为至少2500， 从而避免在随后的热处理期间覆盖的图案化导电层上的保形SiON阻挡层的变形和/或分层。

公开(公告)号：US6124640A

公开(公告)日：2000-09-26

申请号：US144506

申请日：1998-08-31

申请人： Kashmir Sahota ,  Richard J. Huang ,  Hung-Sheng Chen ,  Yu Sun

发明人： Kashmir Sahota ,  Richard J. Huang ,  Hung-Sheng Chen ,  Yu Sun

IPC分类号： H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L51/00

CPC分类号： H01L21/76837 ,  H01L21/76834 ,  H01L21/31051 ,  H01L21/3145 ,  H01L21/31612

摘要： An inter-level dielectric (ILD) is formed from a lower barrier layer comprising a conformal silicon oxynitride layer, a gap fill layer comprising a high-density plasma (HDP) oxide and a cap layer. The use of HDP oxide as a gap fill layer enables better control of the ILD thickness, avoids outgasing problems, facilitates via formation and reduces planarization.

摘要翻译： 层间电介质（ILD）由包括保形氮氧化硅层的下阻挡层，包含高密度等离子体（HDP）氧化物和盖层的间隙填充层形成。 使用HDP氧化物作为间隙填充层能够更好地控制ILD厚度，避免出现问题，便于通孔形成并减少平坦化。