公开(公告)号：US09552890B2

公开(公告)日：2017-01-24

申请号：US14189529

申请日：2014-02-25

Applicant: Freescale Semiconductor, Inc.

Inventor： John M. Pigott ,  Randall C. Gray

IPC: G11C17/06 ,  H01L23/525 ,  G11C17/16 ,  H01L27/112 ,  G11C17/18

CPC classification number: G11C17/16 ,  G11C17/06 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The embodiments described herein provide antifuse devices and methods that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes an antifuse, a first diode coupled with the antifuse in a parallel combination, and a second diode coupled in series with the parallel combination. In such an embodiment the first diode effectively provides a bypass current path that can reduce the voltage across the antifuse when other antifuses are being programmed. As such, these embodiments can provide improved ability to tolerate programming voltages without damage or impairment of reliability.

Abstract translation: 这里描述的实施例提供可以用于各种各样的半导体器件中的反熔丝器件和方法。 在一个实施例中，提供了一种半导体器件，其包括反熔丝，与并联组合中的反熔丝耦合的第一二极管和与并联组合串联耦合的第二二极管。 在这样的实施例中，第一二极管有效地提供旁路电流路径，当其它反熔丝被编程时，可以减小反熔丝两端的电压。 因此，这些实施例可以提供改善的耐受编程电压的能力，而不会损坏或损害可靠性。

公开(公告)号：US09362987B2

公开(公告)日：2016-06-07

申请号：US14812242

申请日：2015-07-29

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Fred T. Brauchler ,  Randall C. Gray

IPC: H01L27/08 ,  H04B5/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/495 ,  H01L29/739 ,  H01L23/64 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/522 ,  H01L23/31

CPC classification number: H04B5/0081 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/49822 ,  H01L23/5227 ,  H01L23/564 ,  H01L23/645 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/50 ,  H01L29/7393 ,  H01L29/7395 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49 ,  H01L2224/73203 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/85801 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/1206 ,  H01L2924/13055 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/20641 ,  H01L2924/20642 ,  H01L2924/20643 ,  H01L2924/20644 ,  H04B5/0031 ,  H04B5/0075 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Embodiments of inductive communication devices include first and second IC die and an inductive coupling substrate. The first IC die has a first coil. The inductive coupling substrate has a second coil and a first signal communication interface (e.g., a third coil or a contact). The second IC die has a second signal communication interface (e.g., a fourth coil or a contact). The first IC die and the inductive coupling substrate are arranged so that the first and second coils are aligned across a gap between the first IC die and the inductive coupling substrate. A dielectric component is positioned within the gap between the first and second coils to galvanically isolate the first IC die and the inductive coupling substrate. During operation, signals are conveyed between the first and second IC die through inductive coupling between the coils and communication through the signal communication interfaces.

Abstract translation: 感应通信设备的实施例包括第一和第二IC芯片和电感耦合衬底。 第一IC芯片具有第一线圈。 电感耦合衬底具有第二线圈和第一信号通信接口（例如，第三线圈或接触件）。 第二IC芯片具有第二信号通信接口（例如，第四线圈或触点）。 第一IC芯片和感应耦合衬底被布置成使得第一和第二线圈跨越第一IC芯片和感应耦合衬底之间的间隙对准。 绝缘元件位于第一和第二线圈之间的间隙内，以使第一IC芯片和感应耦合衬底电隔离。 在操作期间，通过线圈之间的感应耦合和通过信号通信接口进行通信，在第一和第二IC芯片之间传送信号。

公开(公告)号：US09778319B2

公开(公告)日：2017-10-03

申请号：US14536017

申请日：2014-11-07

Applicant: Freescale Semiconductor, Inc.

Inventor： William E. Edwards ,  Anthony F. Andresen ,  Randall C. Gray

IPC: G01R31/02 ,  G01R31/327 ,  G01R19/00 ,  H03K17/18 ,  H02B1/24 ,  G01R19/165

CPC classification number: G01R31/3274 ,  G01R19/16566 ,  G01R31/3275 ,  G01R31/3277

Abstract: The embodiments described herein provide systems and methods for determining the health status of a sensed switch. In general, the embodiments described herein determine a measure of a health status of the sensed switch by comparing a voltage on the sensed switch, ascertaining a first comparator state under one test condition and ascertaining a second comparator state under a second test condition. The first comparator state and the second comparator state are and then compared to determine the measure of the health status of the sensed switch.

公开(公告)号：US09385190B2

公开(公告)日：2016-07-05

申请号：US14196278

申请日：2014-03-04

Applicant: Freescale Semiconductor, Inc.

Inventor： John M. Pigott ,  Brent D. Rogers ,  Randall C. Gray

IPC: H01L29/06 ,  H01L23/525 ,  H01L27/06 ,  H01L21/762 ,  H01L27/02

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/76283 ,  H01L23/5252 ,  H01L27/0207 ,  H01L27/0676 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The embodiments described herein provide a semiconductor device layout and method that can be utilized in a wide variety of semiconductor devices. In one embodiment a semiconductor device is provided that includes a plurality of deep trench isolation structures that define and surround a first plurality of first trench-isolated regions in the substrate, and further define a second plurality of second trench-isolated regions in the substrate. The first plurality of first trench-isolated regions is arranged in a plurality of first columns, with each of the first columns including at least two of the first plurality of first trench-isolated regions. Likewise, the plurality of first columns are interleaved with the second trench-isolated regions to alternate in an array such that a second trench-isolated region is between consecutive first columns in the array and such that at least two first trench-isolated regions are between consecutive second trench-isolated regions in the array.

Abstract translation: 本文描述的实施例提供可用于各种各样的半导体器件的半导体器件布局和方法。 在一个实施例中，提供了半导体器件，其包括多个深沟槽隔离结构，其限定并围绕衬底中的第一多个第一沟槽隔离区域，并且还限定衬底中的第二多个第二沟槽隔离区域。 第一多个第一沟槽隔离区域布置在多个第一列中，其中每个第一列包括第一多个第一沟槽隔离区域中的至少两个。 类似地，多个第一列与第二沟槽隔离区交替排列成阵列中的交替，使得第二沟槽隔离区在阵列中连续的第一列之间，使得至少两个第一沟槽隔离区在 阵列中连续的第二沟槽隔离区域。

公开(公告)号：US09285244B2

公开(公告)日：2016-03-15

申请号：US14723420

申请日：2015-05-27

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： John M. Pigott ,  Fred T. Brauchler ,  William E. Edwards ,  Mike R. Garrard ,  Randall C. Gray ,  John M. Hall

IPC: G01B7/14 ,  G01D5/20 ,  G01P3/488 ,  G01P3/489 ,  G01D5/244

CPC classification number: G01D5/2013 ,  G01D5/24476 ,  G01P3/488 ,  G01P3/489

Abstract: An interface for processing a variable reluctance sensor signal provided by a variable reluctance sensor including an integrator, an arming comparator and a detect circuit. The integrator includes an input for receiving the variable reluctance sensor signal and an output providing an integrated signal indicative of total flux change of the variable reluctance sensor. The arming comparator compares the integrated signal with a predetermined arming threshold and provides an armed signal indicative thereof. The detect circuit provides a reset signal after the armed signal is provided to reset the integrator. A corresponding method of processing the variable reluctance sensor signal is also described.

公开(公告)号：US20150198666A1

公开(公告)日：2015-07-16

申请号：US14152262

申请日：2014-01-10

Applicant: Freescale Semiconductor, Inc.

Inventor： William E. Edwards ,  Anthony F. Andresen ,  Randall C. Gray

IPC: G01R31/327

CPC classification number: G01R31/327 ,  H03K17/18

Abstract: A method of switch detection is disclosed that comprises, enabling a low power mode on a switch detection device, activating a first detection circuit for detecting, at a first expiration of a first polling time interval, a first switch state of a first switch having a first priority level, the first switch state including one of a first open state and a first closed state, comparing the detected first switch state with a prior first switch state, and activating a second detection circuit for detecting, at a second expiration of a second polling time interval, a second switch state of a second switch having a second priority level, the second switch including one of a second open state and a second closed state, and the second polling time interval being greater than the first polling time interval, and the second priority level being different from the first priority level.

Abstract translation: 公开了一种开关检测方法，其特征在于包括：在开关检测装置上实现低功率模式，激活第一检测电路，用于在第一轮询时间间隔的第一次到期时检测具有第一开关的第一开关的第一开关状态， 第一优先级，第一开关状态包括第一打开状态和第一关闭状态之一，将检测到的第一开关状态与先前的第一开关状态进行比较，以及激活第二检测电路，用于在第二优先级的第二次到期时检测 轮询时间间隔，具有第二优先级的第二交换机的第二切换状态，所述第二交换机包括第二打开状态和第二关闭状态中的一个，所述第二轮询时间间隔大于所述第一轮询时间间隔，以及 第二优先级与第一优先级不同。

公开(公告)号：US09329237B2

公开(公告)日：2016-05-03

申请号：US14152262

申请日：2014-01-10

Applicant: Freescale Semiconductor, Inc.

Inventor： William E. Edwards ,  Anthony F. Andresen ,  Randall C. Gray

IPC: H01H36/00 ,  H01H19/18 ,  G01R31/327 ,  H03K17/18

CPC classification number: G01R31/327 ,  H03K17/18

Abstract: A method of switch detection is disclosed that comprises, enabling a low power mode on a switch detection device, activating a first detection circuit for detecting, at a first expiration of a first polling time interval, a first switch state of a first switch having a first priority level, the first switch state including one of a first open state and a first closed state, comparing the detected first switch state with a prior first switch state, and activating a second detection circuit for detecting, at a second expiration of a second polling time interval, a second switch state of a second switch having a second priority level, the second switch including one of a second open state and a second closed state, and the second polling time interval being greater than the first polling time interval, and the second priority level being different from the first priority level.

Abstract translation: 公开了一种开关检测方法，其特征在于包括：在开关检测装置上实现低功率模式，激活第一检测电路，用于在第一轮询时间间隔的第一次到期时检测具有第一开关的第一开关的第一开关状态， 第一优先级，第一开关状态包括第一打开状态和第一关闭状态之一，将检测到的第一开关状态与先前的第一开关状态进行比较，以及激活第二检测电路，用于在第二优先级的第二次到期时检测 轮询时间间隔，具有第二优先级的第二交换机的第二切换状态，所述第二交换机包括第二打开状态和第二关闭状态中的一个，所述第二轮询时间间隔大于所述第一轮询时间间隔，以及 第二优先级与第一优先级不同。