公开(公告)号：US10804170B2

公开(公告)日：2020-10-13

申请号：US16298309

申请日：2019-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang Shen ,  Guoxiang Ning ,  Erfeng Ding ,  Dongsuk Park ,  Xiaoxiao Zhang ,  Lan Yang

IPC: H01L21/66 ,  H01L27/02 ,  H01L27/088 ,  G06F30/20 ,  G06F30/398 ,  G06F111/04 ,  G06F111/20

Abstract: The present disclosure relates to a method which includes generating a device layout of an eBeam based overlay (EBO OVL) structure with a minimum design rule, simulating a worst case process margin for the generated device layout of the EBO OVL structure, enabling a plurality of devices for the simulated worst case process margin for the generated device layout of the EBO OVL structure, and breaking a plurality of design rules for the enabled plurality of devices of the EBO OVL structure to generate an OVL measurement layout of the EBO OVL structure.

公开(公告)号：US20200312764A1

公开(公告)日：2020-10-01

申请号：US16363585

申请日：2019-03-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Ruilong Xie ,  Lei Sun

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: Structures that include interconnects and methods of forming structures that include interconnects. A first interconnect is formed in a first trench in an interlayer dielectric layer, and a second interconnect in a second trench in the interlayer dielectric layer. The second interconnect is aligned along a longitudinal axis with the first interconnect. A dielectric region is arranged laterally arranged between the first interconnect and the second interconnect. The interlayer dielectric layer is composed of a first dielectric material, and the dielectric region is composed of a second dielectric material having a different composition than the first dielectric material.

公开(公告)号：US09606432B2

公开(公告)日：2017-03-28

申请号：US14533464

申请日：2014-11-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guoxiang Ning ,  Xintuo Dai ,  Huang Liu ,  Chin Teong Lim

IPC: G03F7/00 ,  G03F7/09 ,  G03F7/20

CPC classification number: G03F7/0035 ,  G03F7/094 ,  G03F7/2024 ,  G03F7/203

Abstract: Fabrication of a circuit structure is facilitated, in which a first exposure of a multi-layer structure is performed using a first mask, which defines positioning of at least one edge of an element to be formed above a substrate of the multi-layer structure. A second exposure of the multi-layer structure is performed using a second mask, which defines positioning of at least one other edge of the element. At least some material of the multi-layer structure is removed using, at least in part, the defined positioning of the at least one edge and the at least one other edges of the element, to form the element above the substrate. In some examples, multiple elements are formed, the multiple elements being hardmask elements to facilitate an etch process to etch a substrate material.

公开(公告)号：US09535319B2

公开(公告)日：2017-01-03

申请号：US14674157

申请日：2015-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guido Ueberreiter ,  Guoxiang Ning ,  Jui-Hsuan Feng ,  Paul Ackmann ,  Chin Teong Lim

IPC: G03F1/36 ,  G03F7/30 ,  H01L21/768

CPC classification number: G03F1/36

Abstract: A method includes providing a pre-optical proximity correction (OPC) layout of at least a portion of at least one reticle. The pre-OPC layout defines a test cell including a first test cell area having a plurality of first target features having a first pitch and a second test cell area having a plurality of second target features having a second pitch. A post-OPC layout of the portion of the reticle is formed on the basis of the pre-OPC layout. The formation of the post-OPC layout includes performing a rule-based OPC process, wherein a plurality of first reticle features for the first test cell area are provided on the basis of the plurality of first target features, and performing a model-based OPC process, wherein a plurality of second reticle features for the second test cell area are provided on the basis of the plurality of second target features.

Abstract translation: 一种方法包括提供至少一个掩模版的至少一部分的光学前邻近校正（OPC）布局。 预OPC布局定义了包括具有多个具有第一间距的第一目标特征的第一测试单元区域和具有多个具有第二间距的第二目标特征的第二测试单元区域的测试单元。 基于OPC前的布局形成了掩模版部分的后OPC布局。 后OPC布局的形成包括执行基于规则的OPC处理，其中，基于多个第一目标特征提供用于第一测试单元区域的多个第一掩模版特征，并且执行基于模型的OPC 处理，其中，基于所述多个第二目标特征提供用于所述第二测试单元区域的多个第二掩模版特征。

公开(公告)号：US09384318B2

公开(公告)日：2016-07-05

申请号：US14263340

申请日：2014-04-28

Applicant: Globalfoundries Inc.

Inventor： Guoxiang Ning ,  Paul Ackmann ,  Chin Teong Lim

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F7/70441

Abstract: Methodologies and an apparatus for enabling OPC models to account for errors in the mask are disclosed. Embodiments include: determining a patterning layer of a circuit design; estimating a penetration ratio indicating a mask corner rounding error of a fabricated mask for forming the patterning layer in a fabricated circuit; and determining, by a processor, a compensation metric for optical proximity correction of the circuit design based on the penetration ratio.

Abstract translation: 公开了用于使OPC模型能够解决掩模中的错误的方法和装置。 实施例包括：确定电路设计的图形层; 估计在制造的电路中指示用于形成图案化层的制造掩模的掩模角舍入误差的穿透比; 以及基于所述穿透比，由处理器确定所述电路设计的光学邻近校正的补偿度量。

公开(公告)号：US08895211B2

公开(公告)日：2014-11-25

申请号：US13710498

申请日：2012-12-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Guoxiang Ning ,  Chunyu Wong ,  Paul Ackmann ,  Sarasvathi Thangaraju

IPC: G03F1/26

CPC classification number: G03F7/20 ,  G03F1/28 ,  G03F1/42 ,  G03F1/50

Abstract: A mask is disclosed which includes a plurality of first phase shift regions disposed on a first side of the mask, and a plurality of second phase shift regions disposed on a second side of the mask. The first phase shift regions and second phase shift regions may be alternating phase shift regions in which phase shift of the first phase shift regions is out of phase, for instance by 180 degrees, from phase shift of the second phase shift regions. A method for forming the mask, and a semiconductor device fabrication method using the mask is also disclosed.

Abstract translation: 公开了一种掩模，其包括设置在掩模的第一侧上的多个第一相移区域和设置在掩模的第二侧上的多个第二相移区域。 第一相移区域和第二相移区域可以是交变相移区域，其中第一相移区域的相移与第二相移区域的相移相异，例如180度。 还公开了一种形成掩模的方法和使用该掩模的半导体器件制造方法。

公开(公告)号：US10777413B2

公开(公告)日：2020-09-15

申请号：US16033714

申请日：2018-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yuping Ren ,  Guoxiang Ning ,  Haigou Huang ,  Sunil K. Singh

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768

Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer.

公开(公告)号：US20200209166A1

公开(公告)日：2020-07-02

申请号：US16233336

申请日：2018-12-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jed H. Rankin ,  Guoxiang Ning ,  Paul W. Ackmann ,  Jung-Yu Hsieh ,  Ming Lei

IPC: G01N21/956 ,  G06T7/00 ,  G03F7/20

Abstract: A reticle inspection system and related method are disclosed. The system includes a concave spherical mirror positioned adjacent a side of the reticle that is configured to reflect inspection light transmitted through the reticle back towards and through the reticle. A sensor is configured to create at least one of: a first inspection image representative of a circuit pattern of the reticle based on transmission of the inspection light through the first side of the reticle and a reflection thereof by the concave spherical mirror through the second side of the reticle, and a second inspection image representative of the circuit pattern of the reticle based on the reflection of the inspection light from the first side of the reticle. A controller is configured to identify a defect in the reticle based on at least one of the first inspection image and the second inspection image.

公开(公告)号：US10483214B2

公开(公告)日：2019-11-19

申请号：US15860775

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xintuo Dai ,  Dongsuk Park ,  Guoxiang Ning ,  Mert Karakoy

IPC: H01L23/544 ,  H01L21/66 ,  G03F7/20

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to overlay structures and methods of manufacture. The method includes locating a first plurality of offset dummy features in a first layer; locating a second plurality of offset dummy features in a second layer; measuring a distance between the first plurality of offset dummy features and the second plurality of offset dummy features; and determining that the first layer or the second layer is shifted with respect to one another based on the measurement.

公开(公告)号：US10423078B1

公开(公告)日：2019-09-24

申请号：US16398841

申请日：2019-04-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hongliang Shen ,  Erfeng Ding ,  Guoxiang Ning

IPC: G01B11/00 ,  G03F7/20 ,  H01L27/088 ,  H01L21/768 ,  G06F17/50

Abstract: A method to address overlay accuracy compensation using finFET cut isolation revisions is disclosed. For an integrated circuit (IC) layout including at least a portion of an active region including a plurality of gates extending over a plurality of fins, prior to optical proximity correction of the IC layout: the method determines a number of fins to be cut with same source/drain connection by a fin cut isolation opening, and determines a fin cut isolation pitch in the gate length direction of the plurality of gates. The method revises a size of a fin cut isolation opening in the IC layout based on a number of fins to be cut with same source/drain connection by the fin cut isolation opening and the fin cut isolation pitch in the gate length direction. The revision in size of the fin cut isolation compensates for overlay inaccuracy.