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    FORMING AIR GAP
    1.
    发明申请
    FORMING AIR GAP 审中-公开

    公开(公告)号：US20180076082A1

    公开(公告)日：2018-03-15

    申请号：US15813399

    申请日：2017-11-15

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Samuel S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Griselda Bonilla ,  Andrew H. Simon

    IPC: H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L23/528

    CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/31144 ,  H01L23/528 ,  H01L23/5329

    Abstract: A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a dielectric interconnect layer, the dielectric interconnect layer including a dielectric layer having a conductive interconnect therein and a cap layer over the dielectric layer; patterning the air gap mask layer using extreme ultraviolet (EUV) light and etching to form an air gap mask including an opening in the cap layer exposing a portion of the dielectric layer of the dielectric interconnect layer adjacent to the conductive interconnect; removing the air gap mask; etching an air gap space adjacent to the conductive interconnect within the dielectric layer of the dielectric interconnect layer using the opening in the cap layer; and forming an air gap in the dielectric interconnect layer by depositing an air gap capping layer to seal the air gap space.

    Forming air gap
    2.
    发明授权
    Forming air gap 有权

    公开(公告)号：US10224236B2

    公开(公告)日：2019-03-05

    申请号：US15813399

    申请日：2017-11-15

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Samuel S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Griselda Bonilla ,  Andrew H. Simon

    IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L21/02 ,  H01L23/532

    Abstract: A method of forming an air gap for a semiconductor device and the device formed are disclosed. The method may include forming an air gap mask layer over a dielectric interconnect layer, the dielectric interconnect layer including a dielectric layer having a conductive interconnect therein and a cap layer over the dielectric layer; patterning the air gap mask layer using extreme ultraviolet (EUV) light and etching to form an air gap mask including an opening in the cap layer exposing a portion of the dielectric layer of the dielectric interconnect layer adjacent to the conductive interconnect; removing the air gap mask; etching an air gap space adjacent to the conductive interconnect within the dielectric layer of the dielectric interconnect layer using the opening in the cap layer; and forming an air gap in the dielectric interconnect layer by depositing an air gap capping layer to seal the air gap space.

    Hybrid graphene-metal interconnect structures
    3.
    发明授权
    Hybrid graphene-metal interconnect structures 有权
    混合石墨烯 - 金属互连结构

    公开(公告)号：US09257391B2

    公开(公告)日：2016-02-09

    申请号：US13873356

    申请日：2013-04-30

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  Ronald G. Filippi ,  Naftali E. Lustig ,  Andrew H. Simon

    IPC: H01L21/4763 ,  H01L21/44 ,  H01L23/532 ,  H01L23/528 ,  B82Y40/00 ,  B82Y30/00 ,  H01L21/768

    CPC classification number: H01L23/53276 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/76831 ,  H01L21/76838 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  Y10S977/734 ,  Y10S977/842 ,  Y10S977/932 ,  H01L2924/00

    Abstract: Hybrid metal-graphene interconnect structures and methods of forming the same. The structure may include a first end metal, a second end metal, a conductive line including one or more graphene portions extending from the first end metal to the second end metal, and one or more line barrier layers partially surrounding each of the one or more graphene portions. The conductive line may further include one or more intermediate metals separating each of the one or more graphene portions. Methods of forming said interconnect structures may include forming a plurality of metals including a first end metal and a second end metal in a dielectric layer, forming one or more line trenches between each of the plurality of metals, forming a line barrier layer in each of the one or more line trenches, and filling the one or more line trenches with graphene.

    Abstract translation: 混合金属 - 石墨烯互连结构及其形成方法。 该结构可以包括第一端金属，第二端金属，包括从第一端金属延伸到第二端金属的一个或多个石墨烯部分的导电线，以及一个或多个部分围绕一个或多个 石墨烯部分。 导电线还可以包括分离一个或多个石墨烯部分中的每一个的一个或多个中间金属。 形成所述互连结构的方法可以包括在电介质层中形成包括第一端金属和第二端金属的多种金属，在多个金属中的每一个之间形成一个或多个管线沟槽，在每一个中形成线路阻挡层 一个或多个线沟槽，并用石墨烯填充一个或多个线沟槽。

    DETECTING A VOID BETWEEN A VIA AND A WIRING LINE
    5.
    发明申请
    DETECTING A VOID BETWEEN A VIA AND A WIRING LINE 审中-公开
    检测威盛和线路之间的空位

    公开(公告)号：US20160370421A1

    公开(公告)日：2016-12-22

    申请号：US14743208

    申请日：2015-06-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Griselda Bonilla ,  Samuel S. S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Andrew H. Simon

    IPC: G01R31/26 ,  G01R31/02 ,  H01L21/66 ,  H01L23/528 ,  H01L23/522

    CPC classification number: H01L22/12 ,  G01R31/2853 ,  H01L22/14 ,  H01L22/34

    Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and electrically contacting the wiring line. The via induces lateral etching voids between the via and the wiring line below the via upon the surface of the wiring line. The second circuit structure includes a similar wiring line, relative to the reference wiring line, without or fewer via thereupon. The first circuit structure is therefore relatively more prone to lateral etching void formation as compared to the second circuit structure. Resistances are measured across the first circuit structure and the second circuit structure and compared against a comparison threshold to determine whether the first circuit structure includes one or more lateral etching voids. If the first structure is deemed to not include lateral etching voids, the fabrication process of the device may be deemed reliable.

    Abstract translation: 半导体器件包括第一电路结构和第二电路结构。 第一电路结构包括在布线和电接触布线之间的布线和通孔。 该通孔在布线的表面上的通孔下方的通孔和布线之间引起横向蚀刻空隙。 第二电路结构包括相对于参考布线的类似的布线，没有或更少的通孔。 因此，与第二电路结构相比，第一电路结构相对更倾向于侧向蚀刻空隙形成。 在第一电路结构和第二电路结构上测量电阻，并与比较阈值进行比较，以确定第一电路结构是否包括一个或多个横向蚀刻空隙。 如果第一结构被认为不包括侧向蚀刻空隙，则该装置的制造过程可以被认为是可靠的。

    Detecting a void between a via and a wiring line
    7.
    发明授权
    Detecting a void between a via and a wiring line 有权

    公开(公告)号：US10103068B2

    公开(公告)日：2018-10-16

    申请号：US14743208

    申请日：2015-06-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Griselda Bonilla ,  Samuel S. S. Choi ,  Ronald G. Filippi ,  Elbert E. Huang ,  Naftali E. Lustig ,  Andrew H. Simon

    IPC: H01L21/66 ,  G01R31/28

    Abstract: A semiconductor device includes a first circuit structure and a second circuit structure. The first circuit structure includes a wiring line and a via upon and electrically contacting the wiring line. The via induces lateral etching voids between the via and the wiring line below the via upon the surface of the wiring line. The second circuit structure includes a similar wiring line, relative to the reference wiring line, without or fewer via thereupon. The first circuit structure is therefore relatively more prone to lateral etching void formation as compared to the second circuit structure. Resistances are measured across the first circuit structure and the second circuit structure and compared against a comparison threshold to determine whether the first circuit structure includes one or more lateral etching voids. If the first structure is deemed to not include lateral etching voids, the fabrication process of the device may be deemed reliable.

    Structure with air gap crack stop
    8.
    发明授权
    Structure with air gap crack stop 有权
    结构带气隙裂缝停止

    公开(公告)号：US09536842B2

    公开(公告)日：2017-01-03

    申请号：US14574430

    申请日：2014-12-18

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Junjing Bao ,  Griselda Bonilla ,  Samuel S. Choi ,  Ronald G. Filippi ,  Xiao H. Liu ,  Naftali E. Lustig ,  Andrew H. Simon

    IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768

    CPC classification number: H01L23/562 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An method including forming multiple interconnect levels on top of one another, each level comprising a metal interconnect and a crack stop both embedded in a dielectric layer, and a dielectric capping layer directly on top of the dielectric layer and directly on top of the metal interconnect, the crack stop is an air gap which intersects an interface between the dielectric layer and the dielectric capping layer of each interconnect level, and forming a through substrate via through the multiple interconnect levels adjacent to, but not in direct contact with, the crack stop, the crack stop of each interconnect level is directly between the metal interconnect of each interconnect level and the through substrate via to prevent cracks caused during fabrication from propagating away from the through substrate via and damaging the metal interconnect.

    Abstract translation: 一种包括在彼此之上形成多个互连层的方法，每个层包括金属互连和嵌入在电介质层中的裂纹阻挡层，以及直接位于介电层顶部并且直接位于金属互连顶部的电介质覆盖层 裂缝停止是与每个互连层的电介质层和电介质覆盖层之间的界面相交的气隙，并且通过与裂纹停止相邻但不直接接触的多个互连层形成通孔基板通孔 每个互连级别的裂纹停止点直接位于每个互连级别的金属互连和贯通基板通孔之间，以防止制造过程中产生的裂纹从穿过基板传播并损坏金属互连。

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