公开(公告)号：US10593754B2

公开(公告)日：2020-03-17

申请号：US16045267

申请日：2018-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Jerome Ciavatti ,  Jae Gon Lee ,  Josef Watts

IPC: H01L21/265 ,  H01L29/06 ,  H01L21/762

Abstract: Semiconductor structures and methods of forming semiconductor structures. Trench isolation regions arranged to surround an active device region The trench isolation regions extend through a device layer and a buried oxide layer of a silicon-on-insulator wafer into a substrate of the silicon-on-insulator wafer. A well is arranged in the substrate outside of the trench isolation regions, and a doped region is arranged in a portion of the substrate. The doped region is arranged in a portion of the substrate that is located in a horizontal direction adjacent to one of the trench isolation regions and in a vertical direction adjacent to the buried oxide layer. The doped region and the well have the same conductivity type.

公开(公告)号：US20150108586A1

公开(公告)日：2015-04-23

申请号：US14579122

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Johannes M. van Meer

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/78 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66492 ,  H01L29/7833

Abstract: One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.

Abstract translation: 本文公开的一个示例性器件包括位于栅极结构的相对侧上的有源区域中的多个源极/漏极区域，每个源极/漏极区域在晶体管的栅极长度方向上具有横向宽度，并且多个卤素 区域，其中每个光晕区域位于多个源极/漏极区域中的一个的横向宽度的一部分但不是全部的下方。 本文公开的方法包括在有源区域中形成多个晕轮注入区域，其中每个晕轮植入区域的外边缘与隔离区域的相邻内边缘横向间隔开。

公开(公告)号：US08975130B2

公开(公告)日：2015-03-10

申请号：US13930611

申请日：2013-06-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Roderick Miller ,  Marc Tarabbia

IPC: H01L21/8238 ,  H01L27/06 ,  H01L21/8249

CPC classification number: H01L27/0623 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/735 ,  H01L29/7851

Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.

Abstract translation: 本文公开的一种方法包括执行至少一个公共处理操作，以形成用于多个场效应晶体管中的每一个的多个第一栅极结构和在将形成双极晶体管的区域上方的多个第二栅极结构，并且执行离子 注入工艺和加热工艺以形成在所有第二栅极结构下延伸的连续掺杂发射极区域。 本文公开的器件包括具有第一栅极结构的第一多个场效应晶体管，具有位于发射极区域上方的发射极区域和多个第二栅极结构的双极晶体管，其中所述双极晶体管包括延伸的连续掺杂发射极区域 在所有多个第二栅极结构的全部下方。

公开(公告)号：US20140361365A1

公开(公告)日：2014-12-11

申请号：US13912448

申请日：2013-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Yanxiang Liu

IPC: H01L29/78

CPC classification number: H01L29/66575 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: One illustrative device includes a source region and a drain region formed in a substrate, wherein the source/drain regions are doped with a first type of dopant material, a gate structure positioned above the substrate that is laterally positioned between the source region and the drain region and a drain-side well region positioned in the substrate under a portion, but not all, of the entire lateral width of the drain region, wherein the drain-side well region is also doped with the first type of dopant material. The device also includes a source-side well region positioned in the substrate under an entire width of the source region and under a portion, but not all, of the drain region and a part of the extension portion of the drain region is positioned under a portion of the gate structure.

Abstract translation: 一个说明性器件包括形成在衬底中的源极区域和漏极区域，其中源极/漏极区域掺杂有第一类型的掺杂剂材料，位于衬底上方的栅极结构，该栅极结构横向地位于源极区域和漏极 区域和位于衬底中的漏极侧阱区域，其位于漏极区域的整个横向宽度的部分但不是全部，其中漏极侧阱区域还掺杂有第一类型的掺杂剂材料。 该器件还包括源极侧阱区域，其位于源极区域的整个宽度的整个宽度之下且在漏极区域的一部分但不是全部的位置处，并且漏极区域的延伸部分的一部分位于 部分门结构。

公开(公告)号：US10410929B2

公开(公告)日：2019-09-10

申请号：US15860840

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jianwei Peng ,  Yi Qi ,  Hsien-Ching Lo ,  Jerome Ciavatti ,  Ruilong Xie

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L29/66 ,  H01L21/20

Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.

公开(公告)号：US10373877B1

公开(公告)日：2019-08-06

申请号：US15986390

申请日：2018-05-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haiting Wang ,  Hong Yu ,  Hui Zang ,  Wei Zhao ,  Yue Zhong ,  Guowei Xu ,  Laertis Economikos ,  Jerome Ciavatti ,  Scott Beasor

IPC: H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

Abstract: One illustrative method disclosed herein includes forming a plurality of transistors on a semiconductor substrate, wherein each of the transistors comprise source/drain epitaxial semiconductor material in the source/drain regions, a contact etch stop layer (CESL) positioned above the source/drain epitaxial semiconductor material and an insulating material positioned above the contact etch stop layer, and forming a plurality of contact isolation cavities by performing at least one etching process sequence, wherein the etching process sequence is adapted to sequentially remove the insulating material, the CESL and the source/drain epitaxial semiconductor material, and forming a contact isolation structure in each of the contact isolation cavities. In this example, the method also includes, after forming the contact isolation structures, removing the sacrificial gate structures so as to form a plurality of replacement gate cavities, and forming a final gate structure in each of the plurality of replacement gate cavities.

公开(公告)号：US10163635B1

公开(公告)日：2018-12-25

申请号：US15797794

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hui Zang ,  Hsien-Ching Lo ,  Jerome Ciavatti ,  Judson Robert Holt

IPC: H01L21/033 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/861 ,  H01L29/78 ,  H01L49/02

Abstract: A method for preventing epitaxial merge between adjacent devices of a semiconductor is provided. Embodiments include forming a protection layer over a spacer formed over a first and second plurality of fins deposited within a substrate; pinching off a portion of the protection layer formed within a space between each of the plurality of fins; forming a planarization layer over the protection layer and the spacer; and etching a portion of the spacer to form inner sidewalls between each of the plurality of fins, outer sidewalls of a height greater than the height of the inner sidewalls for preventing the growth of the epitaxial layer beyond the outer sidewalls, or a combination thereof.

公开(公告)号：US10026740B1

公开(公告)日：2018-07-17

申请号：US15797533

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Josef Watts

IPC: H01L27/108 ,  H01L29/06

Abstract: One illustrative DRAM structure disclosed herein includes a first memory cell pair, a second memory cell pair, a single diffusion break (SDB) isolation structure positioned between the first and second memory cell pairs, and a single first gate positioned between the first and second memory cell pairs and above the SDB isolation structure.

公开(公告)号：US09601578B2

公开(公告)日：2017-03-21

申请号：US14511769

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Yanxiang Liu ,  Vara Govindeswara Reddy Vakada

IPC: H01L29/66 ,  H01L27/108 ,  H01L21/70 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/06

CPC classification number: H01L29/1095 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/66545 ,  H01L29/66712 ,  H01L29/7809 ,  H01L29/7835

Abstract: A non-planar lateral drift MOS device eliminates the need for a field plate extension, which reduces gate width. In one example, two sources and two comparatively small gates in a raised structure allow for two channels and a dual current with mirrored flows, each traveling into and downward through a center region of a connecting well that connects the substrate with the drain areas and shallow wells containing the source areas, the current then traveling in opposite directions within the substrate region of the connecting well toward the two drains. The source and drain areas may be separate raised structures or isolated areas of a continuous raised structure.

公开(公告)号：US09397191B2

公开(公告)日：2016-07-19

申请号：US14922308

申请日：2015-10-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Yanxiang Liu

IPC: H01L29/66 ,  H01L21/265 ,  H01L29/78 ,  H01L29/08 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/66575 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/0882 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: An isolation region is formed in a semiconductor substrate to laterally define and electrically isolate a device region and first and second laterally adjacent well regions are formed in the device region. A gate structure is formed above the device region such that the first well region extends below an entirety of the gate structure and a well region interface formed between the first and second well regions is laterally offset from a drain-side edge of the gate structure. Source and drain regions are formed in the device region such that the source region extends laterally from a source-side edge of the gate structure and across a first portion of the first well region to a first inner edge of the isolation region and the drain region extends laterally from the drain-side edge and across a second portion of the first well region.

Abstract translation: 在半导体衬底中形成隔离区域以横向限定并电隔离器件区域，并且在器件区域中形成第一和第二横向相邻阱区域。 在器件区域上方形成栅极结构，使得第一阱区域延伸到整个栅极结构的下方，并且形成在第一阱区域和第二阱区域之间的阱区域界面从栅极结构的漏极侧边缘横向偏移。 源极和漏极区域形成在器件区域中，使得源极区域从栅极结构的源极侧边缘横向延伸并跨越第一阱区域的第一部分延伸到隔离区域的第一内部边缘，并且漏极区域 从排水侧边缘横向延伸并穿过第一井区域的第二部分。