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    Semiconductor device having non-magnetic single core inductor and method of producing the same
    1.
    发明授权
    Semiconductor device having non-magnetic single core inductor and method of producing the same 有权
    具有非磁性单芯电感的半导体器件及其制造方法

    公开(公告)号：US09484297B2

    公开(公告)日：2016-11-01

    申请号：US14656770

    申请日：2015-03-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ki Young Lee ,  Moosung M. Chae ,  Woo Sik Kim

    IPC: H01L27/08 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L49/02

    CPC classification number: H01L23/5227 ,  H01L21/02126 ,  H01L21/02362 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295 ,  H01L28/10

    Abstract: Integrated circuits with single core inductors and methods for producing them are provided. Embodiments include forming a trench in a dielectric layer; forming a first metal-oxide hard mask by disposing a metal hard mask and an oxide hard mask over the dielectric layer and in strips in the trench; forming metal line trenches through the first metal-oxide hard mask and into the first dielectric layer on opposite sides of the inductor trench and first vias; filling the first metal line trenches, first vias, and trench; forming another dielectric layer and a second metal-oxide hard mask over the filled trench; forming a second trench through the second metal-oxide hard mask and into the second dielectric layer and second metal line trenches and second vias; and filling the second metal line trenches, second vias, and second trench.

    Abstract translation: 提供具有单芯电感器的集成电路及其制造方法。 实施例包括在电介质层中形成沟槽; 通过在所述电介质层上设置金属硬掩模和氧化物硬掩模，并且在所述沟槽中以条状形成第一金属氧化物硬掩模; 通过所述第一金属氧化物硬掩模形成金属线沟槽并进入所述电感器沟槽和第一通孔的相对侧上的第一介电层; 填充第一金属线沟槽，第一通孔和沟槽; 在填充的沟槽上形成另一介电层和第二金属氧化物硬掩模; 通过第二金属氧化物硬掩模形成第二沟槽并形成第二介电层和第二金属线沟槽和第二通孔; 以及填充第二金属线沟槽，第二通孔和第二沟槽。

    INTEGRATED CIRCUITS WITH CAPACITORS AND METHODS OF PRODUCING THE SAME
    3.
    发明申请
    INTEGRATED CIRCUITS WITH CAPACITORS AND METHODS OF PRODUCING THE SAME 有权
    集成电路与电容器及其生产方法

    公开(公告)号：US20160172432A1

    公开(公告)日：2016-06-16

    申请号：US14699083

    申请日：2015-04-29

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Ki Young Lee ,  Sanggil Bae ,  Tony Joung

    IPC: H01L49/02 ,  H01L23/522 ,  H01L21/768

    CPC classification number: H01L28/60 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a capacitor trench through a dielectric layer, and forming a base layer overlying the dielectric layer and within the capacitor trench. A base layer via gap is formed in the base layer, where the base layer via gap is positioned overlying the dielectric layer and the first contact. A base plate and a shield are formed from the base layer, where the base plate is within the capacitor trench. A capacitor insulating layer is formed overlying the base plate, the base layer, and within the base layer via gap, and a via is formed through the base layer via gap. A second contact and a top plate are simultaneously formed, where the second contact is formed in the via and the top plate is formed in the capacitor trench.

    Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括：通过电介质层形成电容器沟槽，以及形成覆盖介电层和电容器沟槽内的基极层。 基底层通孔间隙形成在基底层中，其中基底层通孔间隙位于覆盖电介质层和第一接触部分上。 从基底层形成基板和屏蔽层，其中基板在电容器沟槽内。 通过间隙，在基板，基底层和基底层之间形成电容器绝缘层，并且通过间隙通过基底层形成通孔。 同时形成第二接触和顶板，其中第二接触形成在通孔中，顶板形成在电容器沟槽中。

    Capacitor and contact structures, and formation processes thereof
    5.
    发明授权
    Capacitor and contact structures, and formation processes thereof 有权

    公开(公告)号：US09679959B2

    公开(公告)日：2017-06-13

    申请号：US14837288

    申请日：2015-08-27

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ki Young Lee ,  Sanggil Bae ,  Jae Ho Joung

    IPC: H01L49/02 ,  H01L27/108

    CPC classification number: H01L28/60 ,  H01L27/10805

    Abstract: Capacitor and contact structures are provided, as well as methods for forming the capacitor and contact structures. The methods include, for instance, providing a layer of conductive material above a conductive structure and above a lower electrode of a capacitor; etching the layer of conductive material to define a conductive material hard mask and an upper electrode of the capacitor, the conductive material hard mask being disposed at least partially above the conductive structure; and forming a first conductive contact structure and a second conductive contact structure, the first conductive contact structure extending through an opening in the conductive material hard mask and conductively contacting the conductive structure, and the second conductive contact structure conductively contacting one of the lower electrode of the capacitor, or the upper electrode of the capacitor.

    Integrated circuits with capacitors and methods of producing the same
    8.
    发明授权
    Integrated circuits with capacitors and methods of producing the same 有权
    具有电容器的集成电路及其制造方法

    公开(公告)号：US09349787B1

    公开(公告)日：2016-05-24

    申请号：US14699083

    申请日：2015-04-29

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Ki Young Lee ,  Sanggil Bae ,  Tony Joung

    IPC: H01L21/768 ,  H01L23/522 ,  H01L49/02

    CPC classification number: H01L28/60 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a capacitor trench through a dielectric layer, and forming a base layer overlying the dielectric layer and within the capacitor trench. A base layer via gap is formed in the base layer, where the base layer via gap is positioned overlying the dielectric layer and the first contact. A base plate and a shield are formed from the base layer, where the base plate is within the capacitor trench. A capacitor insulating layer is formed overlying the base plate, the base layer, and within the base layer via gap, and a via is formed through the base layer via gap. A second contact and a top plate are simultaneously formed, where the second contact is formed in the via and the top plate is formed in the capacitor trench.

    Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括：通过电介质层形成电容器沟槽，以及形成覆盖介电层和电容器沟槽内的基极层。 基底层通孔间隙形成在基底层中，其中基底层通孔间隙位于覆盖电介质层和第一接触部分上。 从基底层形成基板和屏蔽层，其中基板在电容器沟槽内。 通过间隙，在基板，基底层和基底层之间形成电容器绝缘层，并且通过间隙通过基底层形成通孔。 同时形成第二接触和顶板，其中第二接触形成在通孔中，顶板形成在电容器沟槽中。

    HIGH DENSITY SERIAL CAPACITOR DEVICE AND METHODS OF MAKING SUCH A CAPACITOR DEVICE
    9.
    发明申请
    HIGH DENSITY SERIAL CAPACITOR DEVICE AND METHODS OF MAKING SUCH A CAPACITOR DEVICE 有权
    高密度串联电容器装置及制造这种电容器件的方法

    公开(公告)号：US20140159199A1

    公开(公告)日：2014-06-12

    申请号：US13712234

    申请日：2012-12-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ki Young Lee ,  Sanggil Bae ,  Tony Joung

    IPC: H01L49/02

    CPC classification number: H01L29/66181 ,  H01L28/60 ,  H01L29/94

    Abstract: A serial capacitor comprised of a bottom electrode, a top electrode that is conductively coupled the bottom electrode, a middle electrode positioned between the bottom and top electrode, a lower dielectric layer positioned between the bottom and middle electrodes, and an upper dielectric layer positioned between the middle and the electrodes. A method includes forming the bottom electrode in a first layer of insulating material, forming the lower dielectric layer and the middle electrode above the bottom electrode, wherein the middle electrode is positioned in a second layer of insulating material, forming the upper dielectric layer above the middle electrode, forming an opening that exposes a portion of the bottom electrode, and forming the top electrode above the upper dielectric layer, wherein a portion of the top electrode extends through the opening and contacts the bottom electrode.

    Abstract translation: 一种串联电容器，包括底部电极，导电耦合底部电极的顶部电极，位于底部和顶部电极之间的中间电极，位于底部和中间电极之间的下部电介质层，以及位于 中间和电极。 一种方法包括在第一绝缘材料层中形成底部电极，在底部电极之上形成下部电介质层和中间电极，其中中间电极位于第二绝缘材料层中，形成上部电介质层 中间电极，形成露出所述底部电极的一部分的开口，以及在所述上部电介质层的上方形成所述顶部电极，其中所述顶部电极的一部分延伸穿过所述开口并接触所述底部电极。

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