公开(公告)号：US20150255277A1

公开(公告)日：2015-09-10

申请号：US14200197

申请日：2014-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Wei Hua TONG ,  Tien-Ying LUO ,  Yan Ping SHEN ,  Feng ZHOU ,  Jun LIAN ,  Haoran SHI ,  Min-hwa CHI ,  Jin Ping LIU ,  Haiting WANG ,  Seung KIM

IPC: H01L21/02 ,  H01L29/51 ,  H01L21/324 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

Abstract translation: 提供具有一个或多个氮化保形层的鳍式晶体管制造方法和结构，以提高半导体器件的可靠性。 该方法包括例如提供至少一个材料层，该材料层部分地保形地设置在衬底上延伸的翅片上，所述材料层包括栅极电介质层; 以及在所述材料层的暴露表面上进行保形氮化处理，所述共形氮化工艺形成暴露的共形氮化表面。

公开(公告)号：US20160225675A1

公开(公告)日：2016-08-04

申请号：US14611769

申请日：2015-02-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yan Ping SHEN ,  Min-hwa CHI ,  Xusheng WU ,  Weihua TONG ,  Haiting WANG

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L21/3215 ,  H01L21/285

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28568 ,  H01L21/3215 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method of forming RMG multi-WF layers for an nFET and pFET, and the resulting device are provided. Embodiments include forming a Si fin; forming a nFET RMG trench and a pFET RMG trench; forming a first Ti layer in the nFET and pFET RMG trenches; implanting N2 in the first Ti layer vertically at a 0° implant angle in the pFET RMG trench; annealing the N2 implanted first Ti layer to form a TiN layer in the pFET RMG trench; stripping un-reacted Ti of the first Ti layer; forming a second Ti layer in the nFET and pFET RMG trenches; implanting Al or C in the second Ti layer vertically at 0°; annealing the Al or C implanted second Ti layer to form TiAl or TiC at a bottom of the nFET and pFET RMG trenches, respectively; and filling the nFET and pFET RMG trenches with Al or W.

Abstract translation: 提供一种形成用于nFET和pFET的RMG多WF层的方法，以及所得到的器件。 实施例包括形成Si翅片; 形成nFET RMG沟槽和pFET RMG沟槽; 在nFET和pFET RMG沟槽中形成第一Ti层; 在pFET RMG沟槽中以0°注入角垂直注入第一Ti层中的N 2; 对N 2注入的第一Ti层退火以在pFET RMG沟槽中形成TiN层; 剥离第一Ti层的未反应的Ti; 在nFET和pFET RMG沟槽中形成第二Ti层; 在0°垂直方向将Al或C注入第二Ti层; 退火Al或C注入的第二Ti层，分别在nFET和pFET RMG沟槽的底部形成TiAl或TiC; 并用Al或W填充nFET和pFET RMG沟槽。

公开(公告)号：US20150024585A1

公开(公告)日：2015-01-22

申请号：US13946485

申请日：2013-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tien-Ying LUO ,  Feng ZHOU ,  Yan Ping SHEN ,  Haiting WANG ,  Haoran SHI ,  Wei Hua TONG ,  Seung KIM ,  Yong Meng LEE

IPC: H01L21/28

CPC classification number: H01L21/28088 ,  H01L21/28176 ,  H01L29/6659

Abstract: A method includes forming a gate structure by growing an interfacial layer on a substrate, depositing a High K layer on the interfacial layer, depositing a TiN Cap on the High K layer and forming a thin barrier layer on the TiN Cap. The gate structure is annealed.

Abstract translation: 一种方法包括通过在衬底上生长界面层来形成栅极结构，在界面层上沉积高K层，在高K层上沉积TiN帽并在TiN帽上形成薄的阻挡层。 栅极结构退火。

公开(公告)号：US20160190324A1

公开(公告)日：2016-06-30

申请号：US15059793

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hua TONG ,  Tien-Ying LUO ,  Yan Ping SHEN ,  Feng ZHOU ,  Jun LIAN ,  Haoran SHI ,  Min-hwa CHI ,  Jin Ping LIU ,  Haiting WANG ,  Seung KIM

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

公开(公告)号：US20160049488A1

公开(公告)日：2016-02-18

申请号：US14458941

申请日：2014-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yan Ping SHEN ,  Haiting WANG ,  Min-hwa CHI ,  Yong Meng LEE

IPC: H01L29/423 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/105 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11

CPC classification number: H01L29/42376 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

Abstract: A semiconductor structure with wide-bottom and/or wide-top gates includes a semiconductor substrate, a source region(s), a drain region(s) associated with the source region(s), and a gate(s) associated with the source region(s) and the drain region(s) having a top portion and a bottom portion. One of the top portion and the bottom portion of the gate(s) is wider than the other of the top portion and bottom portion. The wide-bottom gate is created using a dummy wide-bottom gate etched from a layer of dummy gate material, creating spacers for the dummy gate, removing the dummy gate material and filling the opening created with conductive material. For the wide-top gate, first and second spacers are included, and instead of removing all the dummy gate material, only a portion is removed, exposing the first spacers. The exposed portion of the first spacers may either be completely or partially removed (e.g., tapered), in order to increase the area of the top portion of the gate to be filled.

Abstract translation: 具有宽底部和/或宽顶部栅极的半导体结构包括半导体衬底，源极区域，与源极区域相关联的漏极区域以及与所述源极区域相关联的栅极 源极区和漏极区具有顶部和底部。 栅极的顶部和底部之一比顶部和底部中的另一个宽。 使用从虚拟栅极材料层蚀刻的虚拟宽底栅极创建宽底栅极，产生用于伪栅极的间隔物，去除虚拟栅极材料并填充由导电材料形成的开口。 对于宽顶栅，包括第一和第二间隔物，而不是去除所有的虚拟栅极材料，仅去除一部分，暴露第一间隔物。 第一间隔件的暴露部分可以被完全或部分地去除（例如，渐缩），以增加要填充的浇口顶部的面积。