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    Front-end-of-line device structure and method of forming such a front-end-of-line device structure
    1.
    发明授权
    Front-end-of-line device structure and method of forming such a front-end-of-line device structure 有权

    公开(公告)号：US10483154B1

    公开(公告)日：2019-11-19

    申请号：US16015351

    申请日：2018-06-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Elliot John Smith ,  Marcus Wolf ,  Carsten Peters ,  Markus Lenski ,  Loic Gaben

    IPC: H01L21/762 ,  H01L21/02 ,  H01L29/06

    Abstract: In various aspects, the present disclosure relates to device structures and a method of forming such a device structure. In some illustrative embodiments herein, a device is provided, including a semiconductor substrate having a first trench formed therein, and a first trench isolation structure formed in the first trench. The first trench isolation structure includes first and second insulating liners formed adjacent inner surfaces of the first trench, wherein the first insulating liner is in direct contact with inner surfaces of the first trench and the second insulating liner is formed directly on the first insulating liner, and a first insulating filling material which at least partially fills the first trench. In some aspects, a thickness of the first insulating liner is greater than a thickness of the second insulating liner.

    METHOD INCLUDING A REMOVAL OF A HARDMASK FROM A SEMICONDUCTOR STRUCTURE AND RINSING THE SEMICONDUCTOR STRUCTURE WITH AN ALKALINE RINSE SOLUTION
    2.
    发明申请
    METHOD INCLUDING A REMOVAL OF A HARDMASK FROM A SEMICONDUCTOR STRUCTURE AND RINSING THE SEMICONDUCTOR STRUCTURE WITH AN ALKALINE RINSE SOLUTION 审中-公开
    包括从半导体结构中去除硬质合金的方法和用碱性溶液冲洗半导体结构

    公开(公告)号：US20140349479A1

    公开(公告)日：2014-11-27

    申请号：US13901778

    申请日：2013-05-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Oliver Mieth ,  Torsten Huisinga ,  Carsten Peters ,  Bernd Hintze ,  Grit Bonsdorf

    IPC: H01L21/768

    CPC classification number: H01L21/76897 ,  C23F1/32 ,  C23F1/38 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814

    Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes an electrically conductive feature including a first metal, a dielectric material provided over the electrically conductive feature and a hardmask. The hardmask includes a hardmask material and is provided over the dielectric material. An opening is provided in the interlayer dielectric and the hardmask. A portion of the electrically conductive feature is exposed at a bottom of the opening. The hardmask is removed. The removal of the hardmask includes exposing the semiconductor structure to an etching solution including hydrogen peroxide and a corrosion inhibitor. After the removal of the hardmask, the semiconductor structure is rinsed. Rinsing the semiconductor structure includes exposing the semiconductor structure to an alkaline rinse solution.

    Abstract translation: 一种方法包括提供半导体结构。 半导体结构包括导电特征，其包括第一金属，设置在导电特征上的介电材料和硬掩模。 硬掩模包括硬掩模材料并且设置在电介质材料上。 在层间电介质和硬掩模中设置开口。 导电特征的一部分暴露在开口的底部。 硬掩模被删除。 去除硬掩模包括将半导体结构暴露于包括过氧化氢和腐蚀抑制剂的蚀刻溶液。 在去除硬掩模之后，冲洗半导体结构。 冲洗半导体结构包括将半导体结构暴露于碱性冲洗溶液中。

    Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
    4.
    发明授权
    Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects 有权
    用于制造在金属触点和互连之间具有覆盖层的集成电路的集成电路和方法

    公开(公告)号：US08932911B2

    公开(公告)日：2015-01-13

    申请号：US13778558

    申请日：2013-02-27

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Torsten Huisinga ,  Carsten Peters ,  Andreas Ott ,  Axel Preusse

    IPC: H01L21/4763 ,  H01L21/82 ,  H01L21/311 ,  H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/02 ,  H01L21/768

    CPC classification number: H01L23/5226 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.

    Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括形成电连接到器件的金属接触结构。 在金属接触结构上选择性地形成覆盖层，并且在覆盖层上沉积层间绝缘材料。 金属硬掩模被沉积并在层间电介质材料上图案化以限定层间电介质材料的暴露区域。 该方法蚀刻层间电介质材料的暴露区域以露出覆盖层的至少一部分。 该方法包括用蚀刻剂去除金属硬掩模，同时封盖层将金属接触结构与蚀刻剂物理分离。 沉积金属以形成通过封盖层电连接到金属接触结构的导电通孔。

    SEMICONDUCTOR DEVICES INCLUDING SI/GE ACTIVE REGIONS WITH DIFFERENT GE CONCENTRATIONS
    5.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING SI/GE ACTIVE REGIONS WITH DIFFERENT GE CONCENTRATIONS 审中-公开

    公开(公告)号：US20190312041A1

    公开(公告)日：2019-10-10

    申请号：US15944885

    申请日：2018-04-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Elliot John Smith ,  Gunter Grasshoff ,  Carsten Peters

    IPC: H01L27/11

    Abstract: In semiconductor devices, some active regions may frequently have to be formed on the basis of a silicon/germanium (Si/Ge) mixture in order to appropriately adjust transistor characteristics, for instance, for P-type transistors. To this end, the present disclosure provides manufacturing techniques and respective devices in which at least two different types of active regions, including Si/Ge material, may be provided with a high degree of compatibility with conventional process strategies. Due to the provision of different germanium concentrations, increased flexibility in adjusting characteristics of transistor elements that require Si/Ge material in their active regions may be achieved.

    METHODS FOR FABRICATING INTEGRATED CIRCUITS
    6.
    发明申请
    METHODS FOR FABRICATING INTEGRATED CIRCUITS 有权
    制作集成电路的方法

    公开(公告)号：US20150235896A1

    公开(公告)日：2015-08-20

    申请号：US14185398

    申请日：2014-02-20

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Oliver Mieth ,  Carsten Peters ,  Torsten Huisinga

    IPC: H01L21/768

    CPC classification number: H01L21/76826 ,  H01L21/3105 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76895

    Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes densifying an upper-surface portion of an ILD layer of dielectric material that overlies a metallization layer above a semiconductor substrate to form a densified surface layer of dielectric material. The densified surface layer and the ILD layer are etched through to expose a metal line of the metallization layer.

    Abstract translation: 提供了制造集成电路的方法。 在一个示例中，用于制造集成电路的方法包括使覆盖在半导体衬底之上的金属化层上的介电材料的ILD层的上表面部分致密化，以形成电介质材料的致密表面层。 蚀刻致密表面层和ILD层以暴露金属化层的金属线。

    INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CAPPING LAYERS BETWEEN METAL CONTACTS AND INTERCONNECTS
    7.
    发明申请
    INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CAPPING LAYERS BETWEEN METAL CONTACTS AND INTERCONNECTS 有权
    集成电路与金属接触和互连之间的嵌入层制造集成电路的方法

    公开(公告)号：US20140239503A1

    公开(公告)日：2014-08-28

    申请号：US13778558

    申请日：2013-02-27

    Applicant: GLOBALFOUNDRIES, INC.

    Inventor： Torsten Huisinga ,  Carsten Peters ,  Andreas Ott ,  Axel Preusse

    IPC: H01L21/768 ,  H01L23/48

    CPC classification number: H01L23/5226 ,  H01L21/76814 ,  H01L21/76849 ,  H01L23/485 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.

    Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括形成电连接到器件的金属接触结构。 在金属接触结构上选择性地形成覆盖层，并且在覆盖层上沉积层间绝缘材料。 金属硬掩模被沉积并在层间电介质材料上图案化以限定层间电介质材料的暴露区域。 该方法蚀刻层间电介质材料的暴露区域以露出覆盖层的至少一部分。 该方法包括用蚀刻剂去除金属硬掩模，同时封盖层将金属接触结构与蚀刻剂物理分离。 沉积金属以形成通过封盖层电连接到金属接触结构的导电通孔。

    Semiconductor devices including Si/Ge active regions with different Ge concentrations
    8.
    发明授权
    Semiconductor devices including Si/Ge active regions with different Ge concentrations 有权

    公开(公告)号：US10522555B2

    公开(公告)日：2019-12-31

    申请号：US15944885

    申请日：2018-04-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Elliot John Smith ,  Gunter Grasshoff ,  Carsten Peters

    IPC: H01L21/02 ,  H01L27/11 ,  H01L21/311

    Abstract: In semiconductor devices, some active regions may frequently have to be formed on the basis of a silicon/germanium (Si/Ge) mixture in order to appropriately adjust transistor characteristics, for instance, for P-type transistors. To this end, the present disclosure provides manufacturing techniques and respective devices in which at least two different types of active regions, including Si/Ge material, may be provided with a high degree of compatibility with conventional process strategies. Due to the provision of different germanium concentrations, increased flexibility in adjusting characteristics of transistor elements that require Si/Ge material in their active regions may be achieved.

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