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    Method of forming a semiconductor structure including a ferroelectric material and semiconductor structure including a ferroelectric transistor
    1.
    发明授权
    Method of forming a semiconductor structure including a ferroelectric material and semiconductor structure including a ferroelectric transistor 有权
    形成包括铁电材料的半导体结构和包括铁电晶体管的半导体结构的方法

    公开(公告)号：US09412600B2

    公开(公告)日：2016-08-09

    申请号：US14471812

    申请日：2014-08-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ralf van Bentum ,  Gunter Grasshoff

    IPC: H01L21/28 ,  H01L27/22 ,  H01L29/51 ,  H01L21/8234

    CPC classification number: H01L21/28291 ,  H01L21/28185 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/1159 ,  H01L27/11592 ,  H01L27/22 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78391

    Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A first protection layer is formed over the semiconductor structure. The first protection layer covers the logic transistor region and the input/output transistor region. At least a portion of the ferroelectric transistor region is not covered by the first protection layer. After the formation of the first protection layer, a ferroelectric transistor dielectric is deposited over the semiconductor structure, the ferroelectric transistor dielectric and the first protection layer are removed from the logic transistor region and the input/output transistor region, an input/output transistor dielectric is formed over the input/output transistor region and a logic transistor dielectric is formed over at least the logic transistor region.

    Abstract translation: 本文公开的说明性方法包括提供半导体结构。 半导体结构包括逻辑晶体管区域，铁电晶体管区域和输入/输出晶体管区域。 在半导体结构上形成第一保护层。 第一保护层覆盖逻辑晶体管区域和输入/输出晶体管区域。 至少一部分铁电晶体管区域不被第一保护层覆盖。 在形成第一保护层之后，在半导体结构上沉积铁电晶体管电介质，将铁电晶体管电介质和第一保护层从逻辑晶体管区域和输入/输出晶体管区域，输入/输出晶体管电介质 形成在输入/输出晶体管区域上，并且在至少逻辑晶体管区域上形成逻辑晶体管电介质。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC MATERIAL AND SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR
    3.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC MATERIAL AND SEMICONDUCTOR STRUCTURE INCLUDING A FERROELECTRIC TRANSISTOR 有权
    形成包括微​​电子晶体的微电子材料和半导体结构的半导体结构的方法

    公开(公告)号：US20160064228A1

    公开(公告)日：2016-03-03

    申请号：US14471812

    申请日：2014-08-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ralf van Bentum ,  Gunter Grasshoff

    IPC: H01L21/28 ,  H01L29/51 ,  H01L21/8234 ,  H01L27/22

    CPC classification number: H01L21/28291 ,  H01L21/28185 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/1159 ,  H01L27/11592 ,  H01L27/22 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/78391

    Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a logic transistor region, a ferroelectric transistor region and an input/output transistor region. A first protection layer is formed over the semiconductor structure. The first protection layer covers the logic transistor region and the input/output transistor region. At least a portion of the ferroelectric transistor region is not covered by the first protection layer. After the formation of the first protection layer, a ferroelectric transistor dielectric is deposited over the semiconductor structure, the ferroelectric transistor dielectric and the first protection layer are removed from the logic transistor region and the input/output transistor region, an input/output transistor dielectric is formed over the input/output transistor region and a logic transistor dielectric is formed over at least the logic transistor region.

    Abstract translation: 本文公开的说明性方法包括提供半导体结构。 半导体结构包括逻辑晶体管区域，铁电晶体管区域和输入/输出晶体管区域。 在半导体结构上形成第一保护层。 第一保护层覆盖逻辑晶体管区域和输入/输出晶体管区域。 至少一部分铁电晶体管区域不被第一保护层覆盖。 在形成第一保护层之后，在半导体结构上沉积铁电晶体管电介质，将铁电晶体管电介质和第一保护层从逻辑晶体管区域和输入/输出晶体管区域，输入/输出晶体管电介质 形成在输入/输出晶体管区域上，并且在至少逻辑晶体管区域上形成逻辑晶体管电介质。

    METHODS OF FORMING A GATE CAP LAYER ABOVE A REPLACEMENT GATE STRUCTURE
    4.
    发明申请
    METHODS OF FORMING A GATE CAP LAYER ABOVE A REPLACEMENT GATE STRUCTURE 审中-公开
    在替代门结构上形成门盖层的方法

    公开(公告)号：US20160056263A1

    公开(公告)日：2016-02-25

    申请号：US14928681

    申请日：2015-10-30

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Gunter Grasshoff ,  Catherine Labelle

    IPC: H01L29/66 ,  H01L21/321 ,  H01L21/311 ,  H01L21/3105

    CPC classification number: H01L29/66545 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/76834 ,  H01L21/76897

    Abstract: A method includes performing a first chemical mechanical polishing process to define a polished replacement gate structure having a dished upper surface, wherein the polished dished upper surface of the polished replacement gate structure has a substantially curved concave configuration. A gate cap layer is formed above the polished replacement gate structure, wherein a bottom surface of the gate cap layer corresponds to the polished dished upper surface of the polished replacement gate structure.

    Abstract translation: 一种方法包括执行第一化学机械抛光工艺以限定具有碟形上表面的经抛光的替换栅极结构，其中抛光的替代栅极结构的抛光抛光上表面具有基本上弯曲的凹形构造。 在抛光的替代栅极结构上方形成栅极覆盖层，其中栅极盖层的底表面对应于抛光的替换栅极结构的抛光抛光上表面。

    SEMICONDUCTOR DEVICES INCLUDING SI/GE ACTIVE REGIONS WITH DIFFERENT GE CONCENTRATIONS
    6.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING SI/GE ACTIVE REGIONS WITH DIFFERENT GE CONCENTRATIONS 审中-公开

    公开(公告)号：US20190312041A1

    公开(公告)日：2019-10-10

    申请号：US15944885

    申请日：2018-04-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Elliot John Smith ,  Gunter Grasshoff ,  Carsten Peters

    IPC: H01L27/11

    Abstract: In semiconductor devices, some active regions may frequently have to be formed on the basis of a silicon/germanium (Si/Ge) mixture in order to appropriately adjust transistor characteristics, for instance, for P-type transistors. To this end, the present disclosure provides manufacturing techniques and respective devices in which at least two different types of active regions, including Si/Ge material, may be provided with a high degree of compatibility with conventional process strategies. Due to the provision of different germanium concentrations, increased flexibility in adjusting characteristics of transistor elements that require Si/Ge material in their active regions may be achieved.

    Semiconductor devices including Si/Ge active regions with different Ge concentrations
    8.
    发明授权
    Semiconductor devices including Si/Ge active regions with different Ge concentrations 有权

    公开(公告)号：US10522555B2

    公开(公告)日：2019-12-31

    申请号：US15944885

    申请日：2018-04-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Elliot John Smith ,  Gunter Grasshoff ,  Carsten Peters

    IPC: H01L21/02 ,  H01L27/11 ,  H01L21/311

    Abstract: In semiconductor devices, some active regions may frequently have to be formed on the basis of a silicon/germanium (Si/Ge) mixture in order to appropriately adjust transistor characteristics, for instance, for P-type transistors. To this end, the present disclosure provides manufacturing techniques and respective devices in which at least two different types of active regions, including Si/Ge material, may be provided with a high degree of compatibility with conventional process strategies. Due to the provision of different germanium concentrations, increased flexibility in adjusting characteristics of transistor elements that require Si/Ge material in their active regions may be achieved.

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