公开(公告)号：US20190259619A1

公开(公告)日：2019-08-22

申请号：US15902098

申请日：2018-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Keith Tabakman

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/49 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.

公开(公告)号：US10734233B2

公开(公告)日：2020-08-04

申请号：US15902098

申请日：2018-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Keith Tabakman

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417

Abstract: In the manufacture of a FinFET device, an isolation architecture is provided between gate and source/drain contact locations. The isolation architecture may include a low-k spacer layer and a contact etch stop layer. The isolation architecture further includes a high-k, etch-selective layer that is adapted to resist degradation during an etch to open the source/drain contact locations. The high-k layer, in conjunction with a self-aligned contact (SAC) capping layer disposed over the gate, forms an improved isolation structure that inhibits short circuits or parasitic capacitance between the gate and source/drain contacts.

公开(公告)号：US20190043758A1

公开(公告)日：2019-02-07

申请号：US15670366

申请日：2017-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Keith Tabakman ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/283 ,  H01L21/768

Abstract: Various novel methods of forming a gate-to-source/drain conductive contact structure and the resulting novel device structures are disclosed. One illustrative method disclosed herein includes performing at least one first etching process to form a recess in a gate structure of a gate of a transistor device so as to expose an innermost surface of a portion of a sidewall spacer positioned adjacent a first sidewall of the gate structure and performing at least one second etching process through at least the recess in the gate structure so as to remove at least a portion of the portion of the sidewall spacer with the exposed innermost surface.

公开(公告)号：US10192791B1

公开(公告)日：2019-01-29

申请号：US15913547

申请日：2018-03-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Man Gu ,  Tao Han ,  Junsic Hong ,  Jiehui Shu ,  Asli Sirman ,  Charlotte Adams ,  Jinping Liu ,  Keith Tabakman

IPC: H01L21/8242 ,  H01L21/8238 ,  H01L21/3105 ,  H01L21/02 ,  H01L29/51 ,  H01L27/092

Abstract: A method of forming a robust low-k sidewall spacer by exposing an upper portion of the spacer to a thermal and plasma treatment prior to downstream processes and resulting device are provided. Embodiments include providing a pair of gates separated by a canyon trench over a substrate, an EPI layer in a bottom of the canyon trench, respectively, and a low-k spacer on each opposing sidewall of the pair; forming a masking layer in a bottom portion of the canyon trench, an upper portion of the low-k spacers exposed; and treating the upper portion of the low-k spacers with a thermal and plasma treatment.

公开(公告)号：US20170287777A1

公开(公告)日：2017-10-05

申请号：US15091138

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Zhiguo Sun ,  Keith Tabakman

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/41725 ,  H01L21/285 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76897 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/66477

Abstract: One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a contact opening, wherein the first layer comprises a contact insulating material, the second layer comprises a metal-containing material and the third layer comprises a conductive cap material, wherein the third layer is positioned above the second layer. The method further includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, forming a conductive material above the third layer and removing portions of the layers of material positioned outside of the contact opening.

公开(公告)号：US09536900B2

公开(公告)日：2017-01-03

申请号：US14284820

申请日：2014-05-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ravikumar Ramachandran ,  Huiling Shang ,  Keith Tabakman ,  Henry K. Utomo ,  Reinaldo A. Vega

IPC: H01L21/84 ,  H01L27/12 ,  H01L21/762 ,  H01L29/10

CPC classification number: H01L27/1211 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/1054

Abstract: A method of manufacturing a semiconductor device, by etching a region of an SOI substrate so that only a portion of the original semiconductor is present above the insulator layer. After etching has occurred, a different semiconductor material is grown in the etched region, and fins are formed. An isolation layer is deposited to a height above that the base semiconductor of the etched region.

Abstract translation: 通过蚀刻SOI衬底的区域使得只有一部分原始半导体存在于绝缘体层之上来制造半导体器件的方法。 在蚀刻发生之后，在蚀刻区域中生长不同的半导体材料，并且形成翅片。 隔离层沉积到高于蚀刻区域的基底半导体的高度。

公开(公告)号：US10580875B2

公开(公告)日：2020-03-03

申请号：US15873565

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Keith Tabakman ,  Viraj Sardesai

IPC: H01L29/417 ,  H01L29/66 ,  H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L27/088 ,  H01L21/8234

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and/or drain metallization features; spacers on sidewalls of the gate structures and composed of a first material and a second material; and contacts in electrical contact with the source and/or drain metallization features, and separated from the gate structures by the spacers.

公开(公告)号：US10297504B2

公开(公告)日：2019-05-21

申请号：US15670366

申请日：2017-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Keith Tabakman ,  Ruilong Xie

IPC: H01L21/283 ,  H01L21/311 ,  H01L21/768 ,  H01L21/8234

Abstract: Various novel methods of forming a gate-to-source/drain conductive contact structure and the resulting novel device structures are disclosed. One illustrative method disclosed herein includes performing at least one first etching process to form a recess in a gate structure of a gate of a transistor device so as to expose an innermost surface of a portion of a sidewall spacer positioned adjacent a first sidewall of the gate structure and performing at least one second etching process through at least the recess in the gate structure so as to remove at least a portion of the portion of the sidewall spacer with the exposed innermost surface.

公开(公告)号：US09831123B2

公开(公告)日：2017-11-28

申请号：US15091138

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Zhiguo Sun ,  Keith Tabakman

IPC: H01L21/76 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/41725 ,  H01L21/285 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76897 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/66477

Abstract: One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a contact opening, wherein the first layer comprises a contact insulating material, the second layer comprises a metal-containing material and the third layer comprises a conductive cap material, wherein the third layer is positioned above the second layer. The method further includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, forming a conductive material above the third layer and removing portions of the layers of material positioned outside of the contact opening.

公开(公告)号：US09613855B1

公开(公告)日：2017-04-04

申请号：US15091196

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Zhiguo Sun ,  Keith Tabakman

IPC: H01L21/768 ,  H01L21/00 ,  H01L21/8238

CPC classification number: H01L21/76859 ,  H01L21/285 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76864 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53238 ,  H01L23/53266

Abstract: A method that includes, among other things, forming first and second contact openings in a layer of insulating material that respectively expose a portion of first and second source/drain (S/D) regions of first and second transistors that are of the opposite type, forming first, second and third layers of material within each of the first and second contact openings, and forming an implant masking layer that masks the first contact opening while leaving the second contact opening exposed for further processing. The method also includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, removing the implant masking layer and forming a conductive material in both the first and second contact openings so as to define first and second MIS contact structures positioned in the first and second contact openings.