公开(公告)号：US09515155B2

公开(公告)日：2016-12-06

申请号：US14136815

申请日：2013-12-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roman Boschke ,  Stefan Flachowsky ,  Maciej Wiatr ,  Christian Schippel

IPC: H01L29/49 ,  H01L21/285 ,  H01L23/62 ,  H01L23/525

CPC classification number: H01L29/4975 ,  H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.

Abstract translation: 电子熔断器用于集成电路，以便在制造后允许电路的实时动态重新编程。 因此提出了一种电熔丝，其中适于在电流通过时被吹塑的金属元件不是由硅化物层组成的，而是一个金属层，其上形成半导体层。 然后在半导体层上形成电介质层，以防止在金属层上形成金属硅化物。 电子熔断器的制造过程可以很容易地集成在HKMG制造流程中。 特别地，完全硅化金属栅极可以与电熔丝一起制造，而不会危及电子熔丝的正确功能。

公开(公告)号：US20170330970A1

公开(公告)日：2017-11-16

申请号：US15153831

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Arkadiusz Malinowski ,  Chung Foong Tan ,  Nicolas Sassiat ,  Maciej Wiatr

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636

Abstract: A method includes providing a semiconductor structure including a substrate, a gate structure over the substrate and a sidewall spacer adjacent the gate structure. The substrate includes a first semiconductor material. A substantially isotropic first etch process removing the first semiconductor material is performed. The first etch process forms an undercut below the sidewall spacer. An anisotropic second etch process removing the first semiconductor material is performed, wherein an etch rate in a thickness direction of the substrate is greater than an etch rate in a horizontal direction that is perpendicular to the thickness direction. A crystallographic third etch process removing the first semiconductor material is performed, wherein an etch rate in a first crystal direction is greater than an etch rate in a second crystal direction. The first, second and third etch processes form a source-side recess and a drain-side recess adjacent the gate structure.

公开(公告)号：US20160071947A1

公开(公告)日：2016-03-10

申请号：US14482839

申请日：2014-09-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Maciej Wiatr ,  Stefan Flachowsky

IPC: H01L29/51 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/516 ,  H01L21/28194 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method disclosed herein includes providing a substrate including a semiconductor material. A first area of the substrate is recessed relative to a second area of the substrate, and an active region of a first transistor is formed in the recessed area. An active region of a second transistor is formed in the second area of the substrate. First and second dummy gate structures are formed over the active regions of the first transistor and the second transistor, respectively. At least a portion of the first and second dummy gate structures is replaced with at least a portion of a gate structure of the first transistor and the second transistor, respectively. The gate structure of the first transistor includes a ferroelectric material, and the gate structure of the second transistor does not include a ferroelectric material.

Abstract translation: 本文公开的方法包括提供包括半导体材料的衬底。 衬底的第一区域相对于衬底的第二区域凹陷，并且在凹陷区域中形成第一晶体管的有源区。 第二晶体管的有源区形成在衬底的第二区域中。 第一和第二伪栅极结构分别形成在第一晶体管和第二晶体管的有源区上。 第一和第二伪栅极结构的至少一部分分别由第一晶体管和第二晶体管的栅极结构的至少一部分替代。 第一晶体管的栅极结构包括铁电材料，并且第二晶体管的栅极结构不包括铁电材料。

公开(公告)号：US20130267044A1

公开(公告)日：2013-10-10

申请号：US13909221

申请日：2013-06-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan-Detlef Kronholz ,  Peter Javorka ,  Maciej Wiatr

IPC: H01L21/66

CPC classification number: H01L22/10 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/7848 ,  Y02P80/30

Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.

Abstract translation: 在基于晶体管的基础上在半导体器件中形成高k金属栅极电极结构时，可以避免在N沟道晶体管的栅电极结构的端部处敏感材料的过度曝光，例如，在 在将应变诱导半导体材料并入P沟道晶体管的有源区域中，从而有助于提高预定晶体管特性和性能的产量。

公开(公告)号：US20150200270A1

公开(公告)日：2015-07-16

申请号：US14156861

申请日：2014-01-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Hermann Sachse ,  Maciej Wiatr

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L29/7816 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575

Abstract: When forming semiconductor devices comprising high performance or low-power field effect transistors, the threshold voltage of the transistors is adjusted by the halo implantation and the source and drain regions are defined by a single implantation step. Thus, the number of process steps is reduced, whereas the electrical characteristics, such as leakage level, and performance of the transistors are maintained compared to conventional transistors.

Abstract translation: 当形成包括高性能或低功率场效应晶体管的半导体器件时，通过光晕注入来调节晶体管的阈值电压，并且通过单个注入步骤限定源极和漏极区域。 因此，与常规晶体管相比，工艺步骤的数量减少，而与诸如泄漏水平的电特性和晶体管的性能保持一致。

公开(公告)号：US09812573B1

公开(公告)日：2017-11-07

申请号：US15153831

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Arkadiusz Malinowski ,  Chung Foong Tan ,  Nicolas Sassiat ,  Maciej Wiatr

IPC: H01L29/78 ,  H01L21/306 ,  H01L29/66 ,  H01L29/08 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/165 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/823425 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636

Abstract: A method includes providing a semiconductor structure including a substrate, a gate structure over the substrate and a sidewall spacer adjacent the gate structure. The substrate includes a first semiconductor material. A substantially isotropic first etch process removing the first semiconductor material is performed. The first etch process forms an undercut below the sidewall spacer. An anisotropic second etch process removing the first semiconductor material is performed, wherein an etch rate in a thickness direction of the substrate is greater than an etch rate in a horizontal direction that is perpendicular to the thickness direction. A crystallographic third etch process removing the first semiconductor material is performed, wherein an etch rate in a first crystal direction is greater than an etch rate in a second crystal direction. The first, second and third etch processes form a source-side recess and a drain-side recess adjacent the gate structure.

公开(公告)号：US09627409B2

公开(公告)日：2017-04-18

申请号：US14982112

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Andrei Sidelnicov ,  Maciej Wiatr

IPC: H01L21/76 ,  H01L27/12 ,  H01L49/02 ,  H01L29/786 ,  H01L29/06 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8258

CPC classification number: H01L27/1207 ,  H01L21/762 ,  H01L21/76805 ,  H01L21/76898 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78675

Abstract: A semiconductor device with a metal-containing layer, a first semiconductor layer, that is formed on top of the metal-containing layer, and a resistor that is formed in the metal-containing layer and that is contacted through the first semiconductor layer is provided. Furthermore, a method of manufacturing a semiconductor device is provided, wherein the method comprises manufacturing of a resistor with the following steps: formation of a metal-containing layer over a wafer, particularly a SOI wafer, formation of a first semiconductor layer on top of the metal-containing layer and formation of a contact through the semiconductor layer to the metal-containing layer.

公开(公告)号：US20160300856A1

公开(公告)日：2016-10-13

申请号：US14982112

申请日：2015-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Andrei Sidelnicov ,  Maciej Wiatr

IPC: H01L27/12 ,  H01L29/786 ,  H01L23/538 ,  H01L21/8258 ,  H01L21/768 ,  H01L21/762 ,  H01L29/66 ,  H01L49/02 ,  H01L29/06

CPC classification number: H01L27/1207 ,  H01L21/762 ,  H01L21/76805 ,  H01L21/76898 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/66757 ,  H01L29/78603 ,  H01L29/78675

Abstract: A semiconductor device with a metal-containing layer, a first semiconductor layer, that is formed on top of the metal-containing layer, and a resistor that is formed in the metal-containing layer and that is contacted through the first semiconductor layer is provided. Furthermore, a method of manufacturing a semiconductor device is provided, wherein the method comprises manufacturing of a resistor with the following steps: formation of a metal-containing layer over a wafer, particularly a SOI wafer, formation of a first semiconductor layer on top of the metal-containing layer and formation of a contact through the semiconductor layer to the metal-containing layer.

Abstract translation: 提供一种具有含金属层的半导体器件，形成在含金属层顶部的第一半导体层和形成在含金属层中并与第一半导体层接触的电阻器 。 此外，提供了一种制造半导体器件的方法，其中该方法包括制造电阻器，具体步骤如下：在晶片上，特别是SOI晶片上形成含金属层，在第一半导体层上形成第一半导体层 含金属层和通过半导体层形成与含金属层的接触。

公开(公告)号：US09263582B2

公开(公告)日：2016-02-16

申请号：US14502428

申请日：2014-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan Kronholz ,  Maciej Wiatr

IPC: H01L27/088 ,  H01L29/78 ,  H01L27/12 ,  H01L27/20 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/7849 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/1203 ,  H01L27/20 ,  H01L29/7843

Abstract: An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.

Abstract translation: 可以基于压电材料提供有效的应变诱导机构，从而通过应用单个概念可以提高不同晶体管类型的性能。 例如，压电材料可以设置在不同晶体管类型的有源区的下方，并且可以适当地连接到电压源，以便获得期望的类型的应变。

公开(公告)号：US20150179753A1

公开(公告)日：2015-06-25

申请号：US14136815

申请日：2013-12-20

Applicant: Globalfoundries Inc.

Inventor： Roman Boschke ,  Stefan Flachowsky ,  Maciej Wiatr ,  Christian Schippel

IPC: H01L29/49 ,  H01L21/285 ,  H01L23/62

CPC classification number: H01L29/4975 ,  H01L23/5256 ,  H01L23/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: E-fuses are used in integrated circuits in order to permit real-time dynamic reprogramming of the circuit after manufacturing. An e-fuse is hereby proposed wherein the metal element adapted to be blown upon passage of a current is not comprised of a silicide layer but is rather a metal layer above which a semiconductor layer is formed. A dielectric layer is then formed on the semiconductor layer, in order to prevent metal silicide from forming over the metal layer. The process of manufacturing the e-fuse can be easily integrated in an HKMG manufacturing flow. In particular, fully silicided metal gates may be manufactured in conjunction with the e-fuse, without jeopardizing the correct functioning of the e-fuse.

Abstract translation: 电子熔断器用于集成电路，以便在制造后允许电路的实时动态重新编程。 因此提出了一种电熔丝，其中适于在电流通过时被吹塑的金属元件不是由硅化物层组成的，而是一个金属层，其上形成半导体层。 然后在半导体层上形成电介质层，以防止在金属层上形成金属硅化物。 电子熔断器的制造过程可以很容易地集成在HKMG制造流程中。 特别地，完全硅化金属栅极可以与电熔丝一起制造，而不会危及电子熔丝的正确功能。