公开(公告)号：US10217846B1

公开(公告)日：2019-02-26

申请号：US15873156

申请日：2018-01-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Min Gyu Sung ,  Chanro Park ,  Steven Soss ,  Hui Zang ,  Xusheng Wu ,  Yi Qi ,  Ajey P. Jacob ,  Murat K. Akarvardar ,  Siva P. Adusumilli ,  Jiehui Shu ,  Haigou Huang ,  John H. Zhang

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L29/423 ,  H01L29/165 ,  H01L29/16 ,  H01L29/78

Abstract: Disclosed are a method of forming vertical field effect transistor(s) and the resulting structure. In the method, five semiconductor layers are formed in a stack by epitaxial deposition. The first and fifth layers are one semiconductor material, the second and fourth layers are another and the third layer is yet another. The stack is patterned into fin(s). Vertical surfaces of the second and fourth layers of the fin(s) are etched to form upper and lower spacer cavities and these cavities are filled with upper and lower spacers. Vertical surfaces of the third layer of the fin(s) are etched to form a gate cavity and this cavity is filled with a gate. Since epitaxial deposition is used to form the semiconductor layers, the thicknesses of these layers and thereby the heights of the spacer cavities and gate cavity and the corresponding lengths of the spacers and gate can be precisely controlled.

公开(公告)号：US10833018B2

公开(公告)日：2020-11-10

申请号：US16502521

申请日：2019-07-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L21/285 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08 ,  H01L27/118

Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.

公开(公告)号：US20190326286A1

公开(公告)日：2019-10-24

申请号：US15958426

申请日：2018-04-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Soss ,  Steven Bentley ,  Daniel Chanemougame ,  Julien Frougier ,  Bipul Paul ,  Lars Liebmann

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.

公开(公告)号：US20210013150A1

公开(公告)日：2021-01-14

申请号：US17039187

申请日：2020-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L21/285 ,  H01L21/8238 ,  H01L23/532 ,  H01L27/092 ,  H01L29/08

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers. The first CB layer is electrically connected adjacent the first end of the CA layer and the second layer is electrically connected adjacent the second end of the CA layer. The first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate. The first metal layer being disposed above each source, each drain, and each gate of the first and second transistors. The CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers. At least one via selectively provides an electrical connection between the CA or CB layers and the at least one metal layer.

公开(公告)号：US10699942B2

公开(公告)日：2020-06-30

申请号：US15961337

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Daniel Chanemougame ,  Steven Soss ,  Lars Liebmann ,  Hui Zang ,  Shesh Mani Pandey

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/528 ,  H01L21/8234 ,  H01L23/522 ,  H01L29/78

Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

公开(公告)号：US20200013684A1

公开(公告)日：2020-01-09

申请号：US16538041

申请日：2019-08-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Soss ,  Steven Bentley

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/768 ,  H01L29/08

Abstract: The present disclosure is directed to various embodiments of a product that includes first and second vertical semiconductor structures for first and second, respectively, vertical transistor devices, and first and second gate structures positioned adjacent the first and second, respectively, vertical semiconductor structures. The product also includes a shared conductive gate plug positioned laterally between the first gate structure and the second gate structure, wherein the shared conductive gate plug is conductively coupled to both the first gate structure and the second gate structure.

公开(公告)号：US11201152B2

公开(公告)日：2021-12-14

申请号：US15958426

申请日：2018-04-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Soss ,  Steven Bentley ,  Daniel Chanemougame ,  Julien Frougier ,  Bipul Paul ,  Lars Liebmann

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/51

Abstract: A semiconductor device at least one first transistor of a first type disposed above a substrate and comprising a channel wider in one cross-section than tall, wherein the first type is a PFET transistor or an NFET transistor; and at least one second transistor of a second type disposed above the at least one first transistor and comprising a channel taller in the one cross-section than wide, wherein the second type is a PFET transistor or an NFET transistor, and the second type is different from the first type. Methods and systems for forming the semiconductor structure.

公开(公告)号：US20190326165A1

公开(公告)日：2019-10-24

申请号：US15961337

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Daniel Chanemougame ,  Steven Soss ,  Lars Liebmann ,  Hui Zang ,  Shesh Mani Pandey

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528

Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

公开(公告)号：US10446451B1

公开(公告)日：2019-10-15

申请号：US16027834

申请日：2018-07-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Soss ,  Steven Bentley

IPC: H01L21/8238 ,  H01L29/08 ,  H01L21/768 ,  H01L29/66

Abstract: The present disclosure is directed to various embodiments of a method for forming replacement gate structures for vertical transistors. One illustrative method disclosed herein includes, among other things, forming first and second vertical semiconductor structures, forming first and second sacrificial spacers adjacent channel regions of the first and second vertical semiconductor structures, respectively, forming a ring spacer adjacent the first and second sacrificial spacers, removing end portions of the ring spacer to expose end portions of the first and second sacrificial spacers, replacing the first sacrificial spacer with a first replacement gate structure including a first gate insulation layer and a first conductive gate material, replacing the second sacrificial spacer with a second replacement gate structure including a second gate insulation layer and a second conductive gate material, removing remaining portions of the ring spacer to define a spacer cavity, and forming a dielectric material in the spacer cavity.

公开(公告)号：US20160268204A1

公开(公告)日：2016-09-15

申请号：US15164114

申请日：2016-05-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC: H01L23/535 ,  H01L29/08 ,  H01L27/092 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/285

CPC classification number: H01L23/535 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0847 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.