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    Gate structure cut after formation of epitaxial active regions
    1.
    发明授权
    Gate structure cut after formation of epitaxial active regions 有权
    形成外延活性区后的门结构切割

    公开(公告)号：US09559009B2

    公开(公告)日：2017-01-31

    申请号：US14876212

    申请日：2015-10-06

    Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

    Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Theodorus E. Standaert ,  Ruilong Xie

    IPC: H01L21/311 ,  H01L21/8234 ,  H01L29/417 ,  H01L27/088 ,  H01L29/08 ,  H01L21/84 ,  H01L29/66

    CPC classification number: H01L21/823437 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785

    Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

    Abstract translation: 形成跨越多个半导体材料部分的栅极结构。 源极区域和漏极区域形成在多个半导体材料部分中，并且形成横向围绕栅极结构的栅极间隔物。 通过选择性外延工艺从源极和漏极区域形成外延有源区。 通过切割掩模和蚀刻将栅极结构和栅极间隔物的组装切成多个部分以形成多个栅极组件。 每个门组件包括栅极结构部分和由栅极结构部分横向隔开的两个分离的栅极间隔部分。 可以从栅极间隔物的侧壁的周围去除外延有源区的一部分，以防止外延有源区中的电短路。 可以使用电介质间隔物或电介质衬垫来限制形成金属半导体合金的区域。

    Forming isolated fins from a substrate
    2.
    发明授权
    Forming isolated fins from a substrate 有权
    从基底形成隔离的翅片

    公开(公告)号：US09418902B2

    公开(公告)日：2016-08-16

    申请号：US14050661

    申请日：2013-10-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Kangguo Cheng ,  Shom S. Ponoth ,  Balasubramanian Pranatharthiharan ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC: H01L21/84 ,  H01L21/762 ,  H01L27/12 ,  H01L29/66

    CPC classification number: H01L21/845 ,  H01L21/32 ,  H01L21/76243 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66795

    Abstract: A method of isolating a semiconductor fin from an underlying substrate including forming a masking layer around a base portion of the fin, forming spacers on a top portion of the fin above the masking layer, removing the masking layer to expose the base portion of the fin, and converting the base portion of the fin to an isolation region that electrically isolates the fin from the substrate. The base portion of the fin may be converted to an isolation region by oxidizing the base portion of the fin, using for example a thermal oxidation process. While converting the base portion of the fin to an isolation region, the spacers prevent the top portion of the fin from also being converted.

    Abstract translation: 一种从下面的衬底隔离半导体鳍片的方法，包括在鳍片的基底部分周围形成掩模层，在掩模层上方的翅片的顶部上形成间隔物，去除掩模层以暴露鳍片的基底部分 ，并且将鳍的基部转换成将鳍与基板电隔离的隔离区。 通过使用例如热氧化工艺，可以通过氧化散热片的基部来将散热片的基部转换成隔离区。 在将翅片的基部转换成隔离区域的同时，间隔物防止鳍的顶部也被转换。

    HYBRID ORIENTATION FIN FIELD EFFECT TRANSISTOR AND PLANAR FIELD EFFECT TRANSISTOR
    6.
    发明申请
    HYBRID ORIENTATION FIN FIELD EFFECT TRANSISTOR AND PLANAR FIELD EFFECT TRANSISTOR 审中-公开
    混合磁场效应晶体管和平面场效应晶体管

    公开(公告)号：US20160126352A1

    公开(公告)日：2016-05-05

    申请号：US14994549

    申请日：2016-01-13

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC: H01L29/78 ,  H01L21/84 ,  H01L29/08 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

    CPC classification number: H01L29/7848 ,  H01L21/76283 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847

    Abstract: A substrate including a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. Semiconductor fins can be formed by patterning a portion of the buried semiconductor layer after removal of the upper insulator layer and the top semiconductor layer in a fin region, while a planar device region is protected by an etch mask. A disposable fill material portion is formed in the fin region, and a shallow trench isolation structure can be formed in the planar device region. The disposable fill material portion is removed, and gate stacks for a planar field effect transistor and a fin field effect transistor can be simultaneously formed. Alternately, disposable gate structures and a planarization dielectric layer can be formed, and replacement gate stacks can be subsequently formed.

    Abstract translation: 提供了包括手柄基板，下绝缘体层，埋入半导体层，上绝缘体层和顶部半导体层的基板。 半导体鳍片可以通过在去除鳍片区域中的上绝缘体层和顶部半导体层之后图案化掩埋半导体层的一部分而形成，而平面器件区域被蚀刻掩模保护。 在翅片区域形成一次性填充材料部分，并且可以在平面装置区域中形成浅沟槽隔离结构。 去除一次性填充材料部分，并且可以同时形成用于平面场效应晶体管和鳍式场效应晶体管的栅极叠层。 或者，可以形成一次性栅极结构和平坦化介电层，并且随后可以形成替换栅极堆叠。

    Passive devices for FinFET integrated circuit technologies
    7.
    发明授权
    Passive devices for FinFET integrated circuit technologies 有权
    FinFET集成电路技术的无源器件

    公开(公告)号：US09236398B2

    公开(公告)日：2016-01-12

    申请号：US14513709

    申请日：2014-10-14

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： William F. Clark, Jr. ,  Robert J. Gauthier, Jr. ,  Terence B. Hook ,  Junjun Li ,  Theodorus E. Standaert ,  Thomas A. Wallner

    IPC: H01L29/66 ,  H01L21/338 ,  H01L27/12 ,  H01L29/78 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/02 ,  H01L21/762 ,  H01L27/092

    CPC classification number: H01L27/1211 ,  H01L21/7624 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0262 ,  H01L27/0924 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785

    Abstract: Device structures and design structures for passive devices that may be used as electrostatic discharge protection devices in fin-type field-effect transistor integrated circuit technologies. A device region is formed in a trench and is coupled with a handle wafer of a semiconductor-on-insulator substrate. The device region extends through a buried insulator layer of the semiconductor-on-insulator substrate toward a top surface of a device layer of the semiconductor-on-insulator substrate. The device region is comprised of lightly-doped semiconductor material. The device structure further includes a doped region formed in the device region and that defines a junction. A portion of the device region is laterally positioned between the doped region and the buried insulator layer of the semiconductor-on-insulator substrate. Another region of the device layer may be patterned to form fins for fin-type field-effect transistors.

    Abstract translation: 无源器件的器件结构和设计结构，可用作鳍式场效应晶体管集成电路技术中的静电放电保护器件。 器件区域形成在沟槽中并且与绝缘体上半导体衬底的处理晶片耦合。 器件区域延伸穿过绝缘体上半导体衬底的掩埋绝缘体层朝向绝缘体上半导体衬底的器件层的顶表面。 器件区域由轻掺杂的半导体材料组成。 器件结构还包括形成在器件区域中并限定结的掺杂区域。 器件区域的一部分横向地位于绝缘体上半导体衬底的掺杂区域和掩埋绝缘体层之间。 可以对器件层的另一区域进行构图以形成翅片型场效应晶体管的鳍片。

    REDUCING GATE HEIGHT VARIATION IN RMG PROCESS
    8.
    发明申请
    REDUCING GATE HEIGHT VARIATION IN RMG PROCESS 审中-公开
    减少闸门高度变化在RMG过程

    公开(公告)号：US20150111373A1

    公开(公告)日：2015-04-23

    申请号：US14057357

    申请日：2013-10-18

    Applicant: GLOBALFOUNDRIES, INC. ,  International Business Machines Corporation

    Inventor： William J. Cote ,  Laertis Economikos ,  Shom Ponoth ,  Theodorus E. Standaert ,  Charan V. Surisetty ,  Ruilong Xie

    IPC: H01L21/8238 ,  H01L21/8234

    CPC classification number: H01L21/823828 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823864

    Abstract: A method of forming transistors is provided. The method includes forming a plurality of transistor structures to have a plurality of dummy gates on a substrate. Each dummy gate is surrounded by sidewall spacers of a height, which is less than the dummy gate and is different for different transistor structures resulting in divots of different depths above the sidewall spacers. The method then deposits a conformal dielectric layer on top of the dummy gates and inside the divots of the plurality of transistor structures with the conformal dielectric layer having a thickness of at least half of a width of the divots, removes only a portion of the conformal dielectric layer that is on top of the dummy gates to expose the dummy gates; and replaces the dummy gates with a plurality of high-k metal gates.

    Abstract translation: 提供一种形成晶体管的方法。 该方法包括形成多个晶体管结构以在衬底上具有多个虚拟栅极。 每个虚拟栅极被高度的侧壁间隔物包围，该间隙小于虚拟栅极，并且对于不同的晶体管结构是不同的，导致在侧壁间隔物上方具有不同深度的裂缝。 该方法然后在保持电介质层的厚度至少为纹理宽度的一半之上的情况下，在虚拟栅极的顶部和多个晶体管结构的纹间之内沉积保形介电层，仅去除一部分保形 位于伪栅极顶部以暴露伪栅极的介电层; 并且用多个高k金属栅极代替伪栅极。

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