公开(公告)号：US09368590B2

公开(公告)日：2016-06-14

申请号：US14073581

申请日：2013-11-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Susan S. Fan ,  Balasubramanian S. Haran ,  David V. Horak ,  Charles W. Koburger

IPC: H01L21/28 ,  H01L21/70 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/42384 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/78651 ,  H01L29/78654

Abstract: A method is provided for fabricating an integrated circuit that includes multiple transistors. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.

Abstract translation: 提供了一种用于制造包括多个晶体管的集成电路的方法。 在半导体层上形成替代栅极叠层，形成栅极间隔物，形成电介质层。 去除虚拟栅极堆叠以形成空腔。 在空腔中形成栅极电介质和功函数金属层。 空腔填充有栅极导体。 门导体和功函数金属层中的仅一个选择性地凹入。 在凹部中形成氧化膜，使得其上表面与电介质层的上表面共面。 氧化膜用于选择性地生长氧化物盖。 形成并蚀刻层间电介质以形成用于源/漏接触的空腔。 源极/漏极接触形成在接触腔中，源极/漏极触点的一部分直接位于氧化物盖上。

公开(公告)号：US09269629B2

公开(公告)日：2016-02-23

申请号：US14528830

申请日：2014-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Tenko Yamashita

IPC: H01L21/76 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L27/088 ,  H01L27/12 ,  H01L21/02 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L27/02

CPC classification number: H01L21/823481 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02227 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/26506 ,  H01L21/26566 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/6681 ,  H01L29/78

Abstract: FinFET structures with dielectric fins and methods of fabrication are disclosed. A gas cluster ion beam (GCIB) tool is used to apply an ion beam to exposed fins, which converts the fins from a semiconductor material such as silicon, to a dielectric such as silicon nitride or silicon oxide. Unlike some prior art techniques, where some fins are removed prior to fin merging, in embodiments of the present invention, fins are not removed. Instead, semiconductor (silicon) fins are converted to dielectric (nitride/oxide) fins where it is desirable to have isolation between groups of fins that comprise various finFET devices on an integrated circuit (IC).

公开(公告)号：US09257531B2

公开(公告)日：2016-02-09

申请号：US14481178

申请日：2014-09-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Soon-Cheon Seo ,  Balasubramanian S. Haran ,  Alexander Reznicek

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/283 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/51

CPC classification number: H01L29/66636 ,  H01L21/0223 ,  H01L21/02636 ,  H01L21/28158 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7833

Abstract: A metallic top surface of a replacement gate structure is oxidized to convert a top portion of the replacement gate structure into a dielectric oxide. After removal of a planarization dielectric layer, selective epitaxy is performed to form a raised source region and a raised drain region that extends higher than the topmost surface of the replacement gate structure. A gate level dielectric layer including a first dielectric material is deposited and subsequently planarized employing the raised source and drain regions as stopping structures. A contact level dielectric layer including a second dielectric material is formed over the gate level dielectric layer, and contact via holes are formed employing an etch chemistry that etches the second dielectric material selective to the first dielectric material. Raised source and drain regions are recessed. Self-aligned contact structures can be formed by filling the contact via holes with a conductive material.

公开(公告)号：US09245965B2

公开(公告)日：2016-01-26

申请号：US14327598

申请日：2014-07-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Balasubramanian S. Haran ,  Sanjay Mehta ,  Shom Ponoth ,  Ravikumar Ramachandran ,  Stefan Schmitz ,  Theodorus E. Standaert

IPC: H01L29/423 ,  H01L27/12 ,  H01L27/088 ,  H01L21/28 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/42364 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/6681

Abstract: A structure including a first plurality of fins and a second plurality of fins etched from a semiconductor substrate, and a fill material located above the semiconductor substrate and between the first plurality of fins and the second plurality of fins, the fill material does not contact either the first plurality of fins or the second plurality of fins.

Abstract translation: 包括从半导体衬底蚀刻的第一多个散热片和第二多个散热片的结构以及位于半导体衬底上方以及第一组散热片和第二组散热片之间的填充材料，填充材料不接触 第一多个翅片或第二多个翅片。

公开(公告)号：US09478549B2

公开(公告)日：2016-10-25

申请号：US14529332

申请日：2014-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Tenko Yamashita

IPC: H01L21/84 ,  H01L27/108 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L27/10826 ,  H01L21/76224 ,  H01L21/76243 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211

Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.

公开(公告)号：US09406790B2

公开(公告)日：2016-08-02

申请号：US14505018

申请日：2014-10-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  James J. Demarest ,  Balasubramanian S. Haran

IPC: H01L29/66 ,  H01L29/775 ,  B82Y10/00 ,  H01L29/06 ,  H01L21/308 ,  H01L29/423 ,  H01L29/786 ,  B82Y40/00 ,  H01L21/02 ,  B82Y99/00

CPC classification number: H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/3086 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/78696 ,  Y10S977/938

Abstract: A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.

Abstract translation: 具有垂直平面的心轴形成在单晶半导体层上。 通过选择性外延在单晶半导体层上形成外延半导体层。 围绕心轴的上部形成第一间隔件。 使用第一间隔物作为蚀刻掩模，外延半导体层垂直凹入。 在第一间隔物的侧壁和外延半导体层的垂直部分上形成第二间隔物。 从外延半导体层的垂直部分的下方蚀刻外延半导体层的水平底部部分，以形成附接到心轴的悬挂的环形半导体鳍片。 使用覆盖心轴的两个端部的图案化掩模层来蚀刻心轴的中心部分。 提供悬挂的半导体鳍片，其由一对支撑结构悬挂。

公开(公告)号：US20160126352A1

公开(公告)日：2016-05-05

申请号：US14994549

申请日：2016-01-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L21/84 ,  H01L29/08 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/76283 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847

Abstract: A substrate including a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. Semiconductor fins can be formed by patterning a portion of the buried semiconductor layer after removal of the upper insulator layer and the top semiconductor layer in a fin region, while a planar device region is protected by an etch mask. A disposable fill material portion is formed in the fin region, and a shallow trench isolation structure can be formed in the planar device region. The disposable fill material portion is removed, and gate stacks for a planar field effect transistor and a fin field effect transistor can be simultaneously formed. Alternately, disposable gate structures and a planarization dielectric layer can be formed, and replacement gate stacks can be subsequently formed.

Abstract translation: 提供了包括手柄基板，下绝缘体层，埋入半导体层，上绝缘体层和顶部半导体层的基板。 半导体鳍片可以通过在去除鳍片区域中的上绝缘体层和顶部半导体层之后图案化掩埋半导体层的一部分而形成，而平面器件区域被蚀刻掩模保护。 在翅片区域形成一次性填充材料部分，并且可以在平面装置区域中形成浅沟槽隔离结构。 去除一次性填充材料部分，并且可以同时形成用于平面场效应晶体管和鳍式场效应晶体管的栅极叠层。 或者，可以形成一次性栅极结构和平坦化介电层，并且随后可以形成替换栅极堆叠。

公开(公告)号：US20140162447A1

公开(公告)日：2014-06-12

申请号：US13709250

申请日：2012-12-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC. ,  RENESAS ELECTRONICS CORPORATION

Inventor： Lisa F. Edge ,  Martin M. Frank ,  Balasubramanian S. Haran ,  Atsuro Inada ,  Sivananda K. Kanakasabapathy ,  Andreas Knorr ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Soon-cheon Seo

IPC: H01L21/28

CPC classification number: H01L29/66795 ,  H01L29/41791

Abstract: A method for fabricating a field effect transistor device includes patterning a fin on substrate, patterning a gate stack over a portion of the fin and a portion of an insulator layer arranged on the substrate, forming a protective barrier over the gate stack, a portion of the fin and a portion of the insulator layer, the protective barrier enveloping the gate stack, depositing a second insulator layer over portions of the fin and the protective barrier, performing a first etching process to selectively remove portions of the second insulator layer to define cavities that expose portions of source and drain regions of the fin without appreciably removing the protective barrier, and depositing a conductive material in the cavities.

Abstract translation: 一种用于制造场效应晶体管器件的方法，包括对衬底上的翅片进行图案化，在栅极堆叠的一部分上构图栅极堆叠，以及布置在衬底上的绝缘体层的一部分，在栅极叠层上形成保护屏障， 所述翅片和所述绝缘体层的一部分，所述保护屏障包围所述栅极堆叠，在所述鳍片和所述保护屏障的部分上沉积第二绝缘体层，执行第一蚀刻工艺以选择性地去除所述第二绝缘体层的部分以限定空腔 其暴露鳍片的源极和漏极区域的部分，而不明显地去除保护屏障，以及在空腔中沉积导电材料。

公开(公告)号：US09548356B2

公开(公告)日：2017-01-17

申请号：US14714779

申请日：2015-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kerber ,  Arvind Kumar ,  Shom Ponoth

IPC: H01L21/70 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

Abstract: Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

Abstract translation: 提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。