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    Via structures for use in semiconductor devices
    1.
    发明授权
    Via structures for use in semiconductor devices 有权

    公开(公告)号：US11222844B2

    公开(公告)日：2022-01-11

    申请号：US16899543

    申请日：2020-06-11

    Applicant: GLOBALFOUNDRIES U.S. INC.

    Inventor： Jun Lian ,  Sipeng Gu ,  Haiting Wang ,  Yanping Shen

    IPC: H01L23/522 ,  H01L43/12 ,  H01L43/02 ,  H01L45/00 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11585

    Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. The present disclosure provides a semiconductor device including a first device region and a second device region. The first device region includes a first metal layer, a first via structure over the first metal layer, a second via structure over the first via structure, and a second metal layer over the second via structure. The first via structure and the second via structure electrically couple the second metal layer to the first metal layer. The second device region includes a third metal layer, a contact structure over the third metal layer, a memory cell structure over the contact structure, and a fourth metal layer over the memory cell structure. The first via structure and the contact structure are made of the same material.

    Middle of line gate structures
    2.
    发明授权
    Middle of line gate structures 有权

    公开(公告)号：US11171237B2

    公开(公告)日：2021-11-09

    申请号：US16386902

    申请日：2019-04-17

    Applicant: GLOBALFOUNDRIES U.S. INC.

    Inventor： Yanping Shen ,  Halting Wang ,  Hui Zang ,  Jiehui Shu

    IPC: H01L23/482 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/8234

    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to middle of line gate structures and methods of manufacture. The structure includes: a plurality of adjacent gate structures; a bridged gate structure composed of a plurality of the adjacent gate structures; source and drain regions adjacent to the bridged gate structure and comprising source and drain metallization features; and contacts to the bridged gate structure and the source and drain metallization features.

    Self-aligned contact
    4.
    发明授权
    Self-aligned contact 有权

    公开(公告)号：US11721728B2

    公开(公告)日：2023-08-08

    申请号：US16777531

    申请日：2020-01-30

    Applicant: GLOBALFOUNDRIES U.S. INC.

    Inventor： Sipeng Gu ,  Jiehui Shu ,  Halting Wang ,  Yanping Shen

    IPC: H01L29/417 ,  H01L29/78

    CPC classification number: H01L29/41775 ,  H01L29/41791 ,  H01L29/7851

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned contacts and methods of manufacture. The structure includes: adjacent diffusion regions located within a substrate material; sidewall structures above an upper surface of the substrate material, aligned on sides of the adjacent diffusion regions; and a contact between the sidewall structures and extending to within the substrate material between and in electrical contact with the adjacent diffusion regions.

    Forming two portion spacer after metal gate and contact formation, and related IC structure
    5.
    发明授权
    Forming two portion spacer after metal gate and contact formation, and related IC structure 有权

    公开(公告)号：US11482456B2

    公开(公告)日：2022-10-25

    申请号：US16360183

    申请日：2019-03-21

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Yanping Shen ,  Hui Zang ,  Jiehui Shu

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/02 ,  H01L27/088 ,  H01L29/49 ,  H01L29/423

    Abstract: A method of forming an IC structure includes providing a metal gate structure, a spacer adjacent the metal gate structure and a contact to each of a pair of source/drain regions adjacent sides of the spacer. The spacer includes a first dielectric having a first dielectric constant. The metal gate structure is recessed, and the spacer is recessed to have an upper surface of the first dielectric below an upper surface of the metal gate structure, leaving a lower spacer portion. An upper spacer portion of a second dielectric having a dielectric constant lower than the first dielectric is formed over the lower spacer portion. A gate cap is formed over the metal gate structure and the upper spacer portion. The second dielectric can include, for example, an oxide or a gas. The method may reduce effective capacitance and gate height loss, and improve gate-to-contact short margin.

    Memory device and methods of making such a memory device
    6.
    发明授权
    Memory device and methods of making such a memory device 有权

    公开(公告)号：US11437568B2

    公开(公告)日：2022-09-06

    申请号：US16836434

    申请日：2020-03-31

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Yanping Shen ,  Haiting Wang ,  Sipeng Gu

    IPC: H01L43/02 ,  H01L27/22 ,  G11C11/16 ,  H01L43/12

    Abstract: One illustrative memory cell disclosed herein includes at least one layer of insulating material having a first opening and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer includes a spacer opening. The memory cell also includes a bottom electrode positioned within the spacer opening, a memory state material positioned above an upper surface of the bottom electrode and above an upper surface of the internal sidewall spacer, and a top electrode positioned above the memory state material.

    Field effect transistor with asymmetric gate structure and method
    7.
    发明授权
    Field effect transistor with asymmetric gate structure and method 有权

    公开(公告)号：US11342453B2

    公开(公告)日：2022-05-24

    申请号：US16996010

    申请日：2020-08-18

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Yanping Shen ,  Haiting Wang ,  Zhiqing Li

    IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423

    Abstract: Disclosed is a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a replacement metal gate (RMG) structure that includes a first section, which traverses a semiconductor body at a channel region in a first-type well, and a second section, which is adjacent to the first section and which traverses the semiconductor body at a drain drift region in a second-type well. The RMG structure includes, in both sections, a first-type work function layer and a second-type work function layer on the first-type work function layer. However, the thickness of the first-type work function layer in the first section is greater than the thickness in the second section such that the RMG structure is asymmetric. Thus, threshold voltage (Vt) at the first section is greater than Vt at the second section and the LDMOSFET has a relatively high breakdown voltage (BV). Also disclosed are methods for forming the LDMOSFET.

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