公开(公告)号：US20150220676A1

公开(公告)日：2015-08-06

申请号：US14687477

申请日：2015-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Soo Han CHOI ,  Li YANG ,  Jongwook KYE

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending horizontally in an IC design, each of the plurality of first routes being placed on one of a plurality of equally spaced vertical positions of the IC design; determining whether a second route overlaps one of the vertical positions of the plurality of equally spaced vertical positions; and selecting a design rule for the second route based on the determination of whether the second route overlaps.

公开(公告)号：US20160378906A1

公开(公告)日：2016-12-29

申请号：US15040235

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Jongwook KYE ,  Harry J. LEVINSON

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  H01L21/027

Abstract: Methods for performing design rule checking of a circuit design are provided. The methods include, for instance: providing a circuit design for an integrated circuit layer, in which the circuit design includes a plurality of design lines oriented in a particular direction; and automatically performing a design rule check of the circuit design, which may include forming a verification pattern for the circuit design, the verification pattern comprising a plurality of verification lines and a plurality of verification regions, wherein one or more verification regions are associated with and connected to one verification line of the plurality of verification lines, and checking the verification pattern for any verification line overlapping a verification region. The circuit design may be considered to fail the design rule check if an end of one verification line overlaps any verification region associated with another verification line of the verification pattern.

Abstract translation: 提供了对电路设计进行设计规则检查的方法。 所述方法包括例如提供用于集成电路层的电路设计，其中电路设计包括沿特定方向定向的多个设计线; 并且自动执行电路设计的设计规则检查，其可以包括形成用于电路设计的验证模式，所述验证模式包括多个验证线和多个验证区域，其中一个或多个验证区域与 连接到多条验证线的一条验证线，并且检查与验证区域重叠的任何验证线的验证模式。 可以认为电路设计不能使设计规则检查一个验证线的末端是否与与验证图案的另一验证线相关联的任何验证区域重叠。

公开(公告)号：US20160293478A1

公开(公告)日：2016-10-06

申请号：US14679060

申请日：2015-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Jongwook KYE ,  Harry J. LEVINSON

IPC: H01L21/768 ,  H01L21/027 ,  H01L23/532 ,  H01L21/311

CPC classification number: H01L21/76802 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257

Abstract: Self-aligned double patterning processes to produce metal route between and connecting conductive lines are disclosed. Embodiments include forming a hard mask over a dielectric layer; forming a patterning template including plural parallel linear elements on the hard mask, wherein said hard mask is exposed between adjacent parallel linear elements; forming a block mask covering a portion of said adjacent parallel linear elements and spaces therebetween; etching exposed portions of said hard mask through said block mask and said patterning template defining plural parallel lines; removing said block mask and said patterning template; forming a cut mask above said hard mask to define an opening perpendicular to and connecting two adjacent parallel lines; etching said hard mask through said cut mask and removing the cut mask; etching recesses in the dielectric layer through said hard mask; removing the hard mask; and filling said recesses with a conductive material.

Abstract translation: 公开了用于在导线之间产生金属路径的自对准双重图案化工艺。 实施例包括在电介质层上形成硬掩模; 在硬掩模上形成包括多个平行线形元件的图案化模板，其中所述硬掩模在相邻的平行线性元件之间露出; 形成覆盖所述相邻的平行线性元件的一部分和其间的空间的块掩模; 通过所述块掩模蚀刻所述硬掩模的暴露部分和限定多条平行线的所述图案化模板; 去除所述块掩模和所述图案化模板; 在所述硬掩模上形成切割掩模以限定垂直于并连接两个相邻平行线的开口; 通过所述切割掩模蚀刻所述硬掩模并除去切割的掩模; 通过所述硬掩模蚀刻介电层中的凹槽; 去除硬面膜; 并用导电材料填充所述凹部。

公开(公告)号：US20160117432A1

公开(公告)日：2016-04-28

申请号：US14523558

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Irene LIN ,  Jongwook KYE ,  Mahbub RASHED

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5077 ,  Y02T10/82

Abstract: A method and apparatus for an assisted metal routing is disclosed. Embodiments may include: determining an initial block mask having a first inner vertex for forming a metal routing layer of an integrated circuit (IC); adding an assistant metal portion within the metal routing layer; and determining a modified block mask based on the assistant metal portion for forming the metal routing layer.

Abstract translation: 公开了一种用于辅助金属布线的方法和装置。 实施例可以包括：确定具有用于形成集成电路（IC）的金属布线层的第一内部顶点的初始块掩模; 在所述金属布线层内添加辅助金属部分; 以及基于用于形成金属布线层的辅助金属部分确定修改的块掩模。

公开(公告)号：US20150213184A1

公开(公告)日：2015-07-30

申请号：US14163511

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Mahbub RASHED ,  Jongwook KYE

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  Y02T10/82

Abstract: A methodology for a modified cell architecture and the resulting devices are disclosed. Embodiments may include determining a first vertical track spacing for a plurality of first routes for an integrated circuit (IC) design, each of the plurality of first routes having a first width, determining a second vertical track spacing for a second route for the IC design, the second route having a second width, and designating a cell vertical dimension for the IC design based on the first and second vertical track spacings.

Abstract translation: 公开了修改的小区体系结构的方法以及所得到的设备。 实施例可以包括确定用于集成电路（IC）设计的多个第一路由的第一垂直轨道间隔，所述多个第一路线中的​​每一条路径具有第一宽度，确定用于IC设计的第二路线的第二垂直轨道间距 所述第二路径具有第二宽度，并且基于所述第一和第二垂直轨道间隔指定所述IC设计的单元垂直尺寸。

公开(公告)号：US20160141291A1

公开(公告)日：2016-05-19

申请号：US14540724

申请日：2014-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Youngtag WOO ,  Myungjun LEE ,  Ryan Ryoung-Han KIM ,  Jongwook KYE

IPC: H01L27/11 ,  H01L23/522 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/1104 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for utilizing metal segments of an additional metal layer as landing pads for vias and also as local interconnects between contacts in an IC device and resulting devices are disclosed. Embodiments include forming source/drain and gate contacts connected to transistors on a substrate in an integrated circuit device, each contact having an upper surface with a first area; forming metal segments in a plane at the upper surface of the contacts, each metal segment being in contact with one or more of the contacts and having a second area greater than the first area; and forming one or more vias between one or more of the metal segments and one or more first segments of a first metal layer.

Abstract translation: 公开了用于利用附加金属层的金属段作为通孔的着陆焊盘以及IC器件中的触点之间的局部互连以及所产生的器件的方法。 实施例包括在集成电路器件中形成连接到衬底上的晶体管的源极/漏极和栅极触点，每个触点具有带有第一区域的上表面; 在触头的上表面处的平面中形成金属段，每个金属段与一个或多个触点接触并具有大于第一区的第二区; 以及在一个或多个金属段和第一金属层的一个或多个第一段之间形成一个或多个通孔。

公开(公告)号：US20150311122A1

公开(公告)日：2015-10-29

申请号：US14263399

申请日：2014-04-28

Applicant: Globalfoundries Inc.

Inventor： Mahbub RASHED ,  Yunfei DENG ,  Juhan KIM ,  Jongwook KYE ,  Suresh VENKATESAN ,  Subramani KENGERI

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886

Abstract: Methods for forming abutting FinFET cells with a single dummy gate and continuous fins, and the resulting devices, are disclosed. Embodiments may include forming one or more continuous fins on a substrate, forming gates perpendicular to and over the one or more continuous fins to form a first FinFET cell and a second FinFET cell, and forming source and drain contact lines parallel to and between the gates, wherein a source contact line of the first FinFET cell is adjacent to a drain contact line of the second FinFET cell, and the source contact line and the drain contact line are on opposite sides of a gate.

Abstract translation: 公开了用于形成具有单个虚拟栅极和连续散热片的邻接FinFET单元的方法以及所得到的器件。 实施例可以包括在基板上形成一个或多个连续的翅片，形成垂直于一个或多个连续翅片上方和上方的栅极以形成第一FinFET单元和第二FinFET单元，以及形成平行于栅极和栅极之间的源极和漏极接触线 ，其中所述第一FinFET单元的源极接触线与所述第二FinFET单元的漏极接触线相邻，并且所述源极接触线和所述漏极接触线位于栅极的相对侧上。

公开(公告)号：US20150067633A1

公开(公告)日：2015-03-05

申请号：US14017594

申请日：2013-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei YUAN ,  Soo Han CHOI ,  Li YANG ,  Jongwook KYE

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: Methodologies and an apparatus enabling a generation of color undeterminable polygons in IC designs are disclosed. Embodiments include: determining a plurality of first routes extending horizontally in an IC design, each of the plurality of first routes being placed on one of a plurality of equally spaced vertical positions of the IC design; determining whether a second route overlaps one of the vertical positions of the plurality of equally spaced vertical positions; and selecting a design rule for the second route based on the determination of whether the second route overlaps.

Abstract translation: 公开了在IC设计中能够产生颜色不可确定的多边形的方法和装置。 实施例包括：确定在IC设计中水平延伸的多个第一路线，所述多条第一路线中的​​每条路线被放置在所述IC设计的多个相等间隔的垂直位置之一上; 确定第二路线是否与所述多个等间隔垂直位置的垂直位置之一重叠; 以及基于所述第二路由是否重叠的确定来选择所述第二路由的设计规则。

公开(公告)号：US20130130161A1

公开(公告)日：2013-05-23

申请号：US13725191

申请日：2012-12-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yunfei DENG ,  Jongwook KYE

IPC: G03F1/00

CPC classification number: G03F1/00 ,  G03B27/42 ,  G03F7/2024 ,  H01L21/0273

Abstract: Methods are provided for fabricating a semiconductor device. One method comprises providing a first pattern having a first polygon, the first polygon having a first tonality and having a first side and a second side, the first side adjacent to a second polygon having a second tonality, and the second side adjacent to a third polygon having the second tonality, and forming a second pattern by reversing the tonality of the first pattern. The method further comprises forming a third pattern from the second pattern by converting the second polygon from the first tonality to the second tonality forming a fourth pattern from the second pattern by converting the third polygon from the first tonality to the second tonality forming a fifth pattern by reversing the tonality of the third pattern, and forming a sixth pattern by reversing the tonality of the fourth pattern.

Abstract translation: 提供了制造半导体器件的方法。 一种方法包括提供具有第一多边形的第一图案，所述第一多边形具有第一音调并且具有第一侧和第二侧，所述第一侧邻近于具有第二音调的第二多边形，并且所述第二侧相邻于第三多边形 具有第二色调的多边形，并且通过反转第一图案的色调来形成第二图案。 该方法还包括通过从第二图案将第二多边形从第一图案转换成第二色调而将第二多边形从第一色调转换成第二色调以从第二图案转换成第二色调，从第二图案形成第三图案， 通过颠倒第三图案的音调，并通过反转第四图案的音调形成第六图案。

公开(公告)号：US20180190588A1

公开(公告)日：2018-07-05

申请号：US15399200

申请日：2017-01-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xuelian ZHU ,  Jia ZENG ,  Wenhui WANG ,  Youngtag WOO ,  Jongwook KYE

IPC: H01L23/535 ,  H01L29/417 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L23/535 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0642 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.