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    SERDES WITH HIGH-BANDWITH LOW-LATENCY CLOCK AND DATA RECOVERY
    2.
    发明申请
    SERDES WITH HIGH-BANDWITH LOW-LATENCY CLOCK AND DATA RECOVERY 有权
    具有高带宽低延迟时钟和数据恢复的SERDES

    公开(公告)号：US20170078084A1

    公开(公告)日：2017-03-16

    申请号：US15162402

    申请日：2016-05-23

    Applicant: INPHI CORPORATION

    Inventor： Simon FOREY ,  Parmanand MISHRA

    IPC: H04L7/033

    CPC classification number: H04L7/0331 ,  H03L7/087 ,  H03M9/00 ,  H04L7/033

    Abstract: The present application is directed to data communication. More specifically, embodiments of the present invention provide a SerDes system that includes multiple communication lanes that are aligned using a clock signal. Each of the communication lanes comprises a receiver, a buffer, and a transmitter. The receiver uses multiple sampling lanes for data sampling and clock recovery. Sampled data are stored at the buffer and transmitted by the transmitter. There are other embodiments as well.

    Abstract translation: 本申请涉及数据通信。 更具体地，本发明的实施例提供了一种SerDes系统，其包括使用时钟信号对准的多个通信通道。 每个通信通道包括接收器，缓冲器和发射器。 接收机使用多个采样通道进行数据采样和时钟恢复。 采样数据存储在缓冲区并由发送器发送。 还有其它实施例。

    HIGH-SPEED CLOCK SKEW CORRECTION FOR SERDES RECEIVERS
    3.
    发明申请
    HIGH-SPEED CLOCK SKEW CORRECTION FOR SERDES RECEIVERS 有权
    SER SERIES接收机的高速时钟修正

    公开(公告)号：US20160373242A1

    公开(公告)日：2016-12-22

    申请号：US15252057

    申请日：2016-08-30

    Applicant: INPHI CORPORATION

    Inventor： Parmanand MISHRA ,  Simon FOREY

    IPC: H04L7/00 ,  H03L7/08 ,  H03K5/135 ,  H04L7/033 ,  H04B1/40

    CPC classification number: H04L7/0079 ,  H03K5/135 ,  H03K2005/00052 ,  H03L7/0807 ,  H04B1/10 ,  H04B1/40 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/06 ,  H04L7/10

    Abstract: The present invention is directed to data communication. More specifically, the present invention provides a mechanism for determining an adjustment delay that minimizes skew error due to poor alignment between edge samples and data samples. The adjustment delay is determined by sampling edge samples and data samples using different test delays at a calibration frequency that is different from the sampling frequency. The test delay associated with the least average position between the data samples and edge samples is selected as the adjustment delay. The adjustment delay is used as a parameter when sampling data at the sampling frequency. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信。 更具体地，本发明提供了一种用于确定最小化由于边缘样本和数据样本之间的不良对准导致的偏斜误差的调整延迟的机制。 调整延迟由采样边缘样本和采样频率不同的不同测试延迟采样数据样本确定。 选择与数据样本和边缘样本之间的最小平均位置相关联的测试延迟作为调整延迟。 当以采样频率采样数据时，调整延迟用作参数。 还有其它实施例。

    CONTINUOUS TIME LINEAR EQUALIZATION FOR CURRENT-MODE LOGIC WITH TRANSFORMER
    10.
    发明申请
    CONTINUOUS TIME LINEAR EQUALIZATION FOR CURRENT-MODE LOGIC WITH TRANSFORMER 有权
    具有变压器的电流模式逻辑的连续时间线性均衡

    公开(公告)号：US20170078120A1

    公开(公告)日：2017-03-16

    申请号：US15359338

    申请日：2016-11-22

    Applicant: INPHI CORPORATION

    Inventor： Parmanand MISHRA ,  Steffen NIELSEN ,  Michael S. HARWOOD

    IPC: H04L25/03 ,  H04L25/02

    CPC classification number: H04L25/03057 ,  H03K19/094 ,  H04L25/0272 ,  H04L25/03885

    Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a CML that uses one or more equalization modules to apply equalization via secondary windings of transformers that are coupled, directly or indirectly, to the CML outputs. The equalization modules comprises a DAC component that generates switching signals based on control signals received from an external equalization module. The equalization module also includes switchable resistors and/or capacitors. The switching signals are used to select switchable resistors and/or capacitors. By switching resistors and/or capacitors at the equalization module, the outputs of the CML are equalized. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信系统和方法。 更具体地说，本发明的实施例提供一种使用一个或多个均衡模块通过直接或间接耦合到CML输出的变压器的次级绕组来施加均衡的CML。 均衡模块包括基于从外部均衡模块接收的控制信号产生开关信号的DAC组件。 均衡模块还包括可切换电阻器和/或电容器。 开关信号用于选择可切换电阻和/或电容器。 通过在均衡模块处切换电阻器和/或电容器，CML的输出相等。 还有其它实施例。

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