公开(公告)号：US11664294B2

公开(公告)日：2023-05-30

申请号：US16241158

申请日：2019-01-07

Applicant: INTEL CORPORATION

Inventor： Aastha Uppal ,  Je-Young Chang ,  Weihua Tang ,  Minseok Ha

IPC: H01L21/56 ,  H01L23/34 ,  H01L23/427 ,  H01L23/00 ,  H01L23/552 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/427 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/09 ,  H01L24/17 ,  H01L24/73 ,  H01L24/81 ,  H01L2924/14

Abstract: An integrated circuit assembly may be formed using a phase change material as an electromagnetic shield and as a heat dissipation mechanism for the integrated circuit assembly. In one embodiment, the integrated circuit assembly may comprise an integrated circuit package including a first substrate having a first surface and an opposing second surface, and at least one integrated circuit device having a first surface and an opposing second surface, wherein the at least one integrated circuit device is electrically attached by the first surface thereof to the first surface of the first substrate; and a phase change material formed on the integrated circuit package.

公开(公告)号：US20210235596A1

公开(公告)日：2021-07-29

申请号：US16750217

申请日：2020-01-23

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Je-Young Chang ,  Ravindranath Mahajan

IPC: H05K7/20

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device comprising a main body portion and a resilient portion extending from the main body portion, wherein the resilient portion has a plurality of extensions, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a stiffener attached to the electronic substrate, wherein at least a portion of the plurality of extensions of the resilient portion of the heat dissipation device are biased against the stiffener.

公开(公告)号：US20200273768A1

公开(公告)日：2020-08-27

申请号：US16287668

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Kumar Singh

IPC: H01L23/31 ,  H01L23/532 ,  H01L23/34 ,  H01L23/00 ,  H01L21/56

Abstract: IC packages including a heat spreading material comprising crystalline carbon. The heat spreading material may be applied directly to an IC die surface, for example at a die prep stage, prior to an application or build-up of packaging material, so that the high thermal conductivity may best mitigate any hot spots that develop at the IC die surface during operation. The heat spreading material may be applied to surface of the IC die.

公开(公告)号：US12021016B2

公开(公告)日：2024-06-25

申请号：US16898196

申请日：2020-06-10

Applicant: Intel Corporation

Inventor： Chandra Mohan Jha ,  Pooya Tadayon ,  Aastha Uppal ,  Weihua Tang ,  Paul Diglio ,  Xavier Brun

IPC: H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L23/373 ,  H01L23/522

CPC classification number: H01L23/49833 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3732 ,  H01L23/3738 ,  H01L23/5226

Abstract: Embodiments disclosed herein comprise a die and methods of forming a die. In an embodiment, a die comprises, a die substrate, wherein the die substrate has a first thermal conductivity, and a first layer over the die substrate, wherein the first layer has a second thermal conductivity that is greater than the first thermal conductivity. In an embodiment, the die further comprises a second layer over the first layer, wherein the second layer comprises transistors.

公开(公告)号：US11769753B2

公开(公告)日：2023-09-26

申请号：US16051065

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： George Vakanas ,  Aastha Uppal ,  Shereen Elhalawaty ,  Aaron McCann ,  Edvin Cetegen ,  Tannaz Harirchian ,  Saikumar Jayaraman

IPC: H01L25/065 ,  H01L23/373 ,  H01L23/367 ,  H01L23/00 ,  H10B12/00

CPC classification number: H01L25/0657 ,  H01L23/367 ,  H01L23/3736 ,  H01L24/49 ,  H10B12/00

Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.

公开(公告)号：US11735495B2

公开(公告)日：2023-08-22

申请号：US16287653

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal

IPC: H01L23/46 ,  F28D15/02 ,  H01L21/48 ,  H01L23/427

CPC classification number: H01L23/46 ,  F28D15/02 ,  H01L21/4882 ,  H01L23/427

Abstract: Package assemblies with a molded substrate comprising fluid conduits. The fluid conduits may be operable for conveying a fluid (e.g., liquid and/or vapor) through some portion of the package substrate structure. Fluid conduits may be at least partially defined by an interconnect trace comprising a metal. The fluid conveyance may improve thermal management of the package assembly, for example removing heat dissipated by one or more integrated circuits (ICs) of the package assembly.

公开(公告)号：US20200273775A1

公开(公告)日：2020-08-27

申请号：US16287653

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Omkar Karhade ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal

IPC: H01L23/46 ,  H01L23/427 ,  H01L21/48 ,  F28D15/02

Abstract: Package assemblies with a molded substrate comprising fluid conduits. The fluid conduits may be operable for conveying a fluid (e.g., liquid and/or vapor) through some portion of the package substrate structure. The fluid conveyance may improve thermal management of the package assembly, for example removing heat dissipated by one or more integrated circuits (ICs) of the package assembly.

公开(公告)号：US20200219789A1

公开(公告)日：2020-07-09

申请号：US16241108

申请日：2019-01-07

Applicant: Intel Corporation

Inventor： Aastha Uppal ,  Je-Young Chang ,  Javed Shaikh ,  Divya Mani ,  Weihua Tang

IPC: H01L23/427 ,  H01L23/522 ,  H01L21/48 ,  H01L23/00

Abstract: An integrated circuit structure may be formed using a phase change material to substantially fill at least one chamber within the integrated circuit assembly to increase thermal capacitance. The integrated circuit assembly may comprise a substrate, at least one integrated circuit device electrically attached to the substrate, a heat dissipation device, a thermal interface material between the integrated circuit device and the heat dissipation device, a chamber defined by the heat dissipation device, the substrate, and the integrated circuit device, and a phase change material within the chamber.

公开(公告)号：US11721607B2

公开(公告)日：2023-08-08

申请号：US16750213

申请日：2020-01-23

Applicant: INTEL CORPORATION

Inventor： Aastha Uppal ,  Je-Young Chang

IPC: H01L23/42 ,  H01L21/56

CPC classification number: H01L23/42 ,  H01L21/56

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, at least one integrated circuit device electrically attached to the electronic substrate, a heat dissipation device, a thermal interface material between the at least one integrated circuit device and the heat dissipation device, and a metal foam surrounding the at least one integrated circuit device and contacting the thermal interface material. The integrated circuit assembly may further include a stiffener attached to the electronic substrate and surrounding the at least one integrated circuit device, wherein the metal foam is disposed between the stiffener, the at least one integrated circuit device, the electronic substrate, and the heat dissipation device.

公开(公告)号：US11387175B2

公开(公告)日：2022-07-12

申请号：US16059535

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Debendra Mallik ,  Sanka Ganesan ,  Pilin Liu ,  Shawna Liff ,  Sri Chaitra Chavali ,  Sandeep Gaan ,  Jimin Yao ,  Aastha Uppal

IPC: H01L23/28 ,  H01L23/34 ,  H01L23/538 ,  H01L23/532 ,  H01L23/498

Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.