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    DYNAMICALLY CHANGING LOCKSTEP CONFIGURATION
    1.
    发明申请
    DYNAMICALLY CHANGING LOCKSTEP CONFIGURATION 有权
    动态更改LOCKSTEP配置

    公开(公告)号：US20160232063A1

    公开(公告)日：2016-08-11

    申请号：US14672131

    申请日：2015-03-28

    Applicant: Intel Corporation

    Inventor： Debaleena Das ,  George H. Huang ,  Jing Ling ,  Reza E. Daftari ,  Meera Ganesan

    IPC: G06F11/16 ,  G06F3/06 ,  G06F11/20

    CPC classification number: G06F11/1662 ,  G06F3/0619 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0683 ,  G06F11/1004 ,  G06F11/108 ,  G06F11/1666 ,  G06F11/20 ,  G06F11/2094 ,  G06F2201/825

    Abstract: Memory subsystem error management enables dynamically changing lockstep partnerships. A memory subsystem has a lockstep partnership relationship between a first memory portion and a second memory portion to spread error correction over the pair of memory resources. The lockstep partnership can be preconfigured. In response to detecting a hard error in the lockstep partnership, the memory subsystem can cancel or reverse the lockstep partnership between the first memory portion and the second memory portion and create or set a new lockstep partnership. The detected error can be a second hard error in the lockstep partnership. The memory subsystem can create new lockstep partnerships between the first memory portion and a third memory portion as lockstep partners and between the second memory portion and a fourth memory portion as lockstep partners. The memory subsystem can also be configured to change the granularity of the lockstep partnership when changing partnerships.

    Abstract translation: 内存子系统错误管理可实现动态更改的锁步合作伙伴关系。 存储器子系统在第一存储器部分和第二存储器部分之间具有锁步合作关系，以在所述一对存储器资源上扩展纠错。 锁定合作伙伴关系可以预先配置。 响应于检测锁步伙伴关系中的硬错误，存储器子系统可以取消或反转第一存储器部分和第二存储器部分之间的锁步合作关系，并且创建或设置新的锁步伙伴关系。 检测到的错误可能是锁步伙伴关系中的第二个硬错误。 存储器子系统可以在第一存储器部分和第三存储器部分之间创建新的锁步合作关系，作为锁步伙伴，并且在第二存储器部分和作为锁步伙伴的第四存储器部分之间。 内存子系统也可以配置为在更改合作伙伴关系时更改锁步伙伴关系的粒度。

    Fast boot up memory controller
    3.
    发明授权
    Fast boot up memory controller 有权

    公开(公告)号：US10552643B2

    公开(公告)日：2020-02-04

    申请号：US15392912

    申请日：2016-12-28

    Applicant: INTEL CORPORATION

    Inventor： John V. Lovelace ,  Sreenivas Mandava ,  Debaleena Das

    IPC: G06F21/79

    Abstract: A method performed by a memory controller is described. The method includes, during boot up, issuing a command to a memory to cause the memory to zero out its content. The method also includes bypassing a descrambler when reading from a location in the memory that has not had its zeroed out content written over the scrambled data. The method also includes processing read data with the descrambler when reading from a location in the memory that has had its zeroed out content written over with scrambled data.

    EXTRACTING SELECTIVE INFORMATION FROM ON-DIE DYNAMIC RANDOM ACCESS MEMORY (DRAM) ERROR CORRECTION CODE (ECC)
    10.
    发明申请
    EXTRACTING SELECTIVE INFORMATION FROM ON-DIE DYNAMIC RANDOM ACCESS MEMORY (DRAM) ERROR CORRECTION CODE (ECC) 有权
    从片上动态随机访问存储器（DRAM）提取选择信息错误修正代码（ECC）

    公开(公告)号：US20160283318A1

    公开(公告)日：2016-09-29

    申请号：US14670413

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Debaleena Das ,  Bill Nale ,  Kuljit S. Bains ,  John B. Halbert

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1048 ,  G06F11/00 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1084

    Abstract: Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

    Abstract translation: 存储器子系统中的错误校正包括在执行内部错误检测和校正之后产生内部校验位的存储器件，以及向内存控制器提供内部校验位。 存储器件执行内部错误检测以响应于来自存储器控制器的读取请求来检测读取数据中的错误。 如果在读取的数据中检测到错误，则存储器件选择性地执行内部纠错。 在执行内部错误检测和校正之后，存储器件产生指示读取数据的错误向量的校验位，并且响应于读取请求将校验位与读取的数据提供给存储器控制器。 存储器控制器可以将校验位应用于存储器件外部的纠错。

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