中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

41 records (took 0.016 seconds)

    DIE-TO-DIE INTERCONNECT
    1.
    发明申请
    DIE-TO-DIE INTERCONNECT 有权

    公开(公告)号：US20220342840A1

    公开(公告)日：2022-10-27

    申请号：US17852865

    申请日：2022-06-29

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Swadesh Choudhary ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

    IPC: G06F13/42

    Abstract: A port is to couple to another die over a die-to-die (D2D) link and includes physical layer (PHY) circuitry including a first number of sideband lanes to carry data for use in training and management of the D2D link, and a second number of mainband lanes to implement a main data path of the D2D link. The mainband lanes include a forwarded clock lane, a valid lane, and a plurality of data lanes. A logical PHY coordinates functions of the sideband lanes and the mainband lanes.

    POWER-FORWARDING BRIDGE FOR INTER-CHIP DATA SIGNAL TRANSFER
    2.
    发明申请
    POWER-FORWARDING BRIDGE FOR INTER-CHIP DATA SIGNAL TRANSFER 有权

    公开(公告)号：US20220199537A1

    公开(公告)日：2022-06-23

    申请号：US17127304

    申请日：2020-12-18

    Applicant: Intel Corporation

    Inventor： Zhiguo Qian ,  Gerald Pasdast ,  Peipei Wang ,  Daniel Krueger ,  Edward Burton

    IPC: H01L23/538 ,  H01L23/50 ,  H01L25/065 ,  H01L21/50

    Abstract: An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.

    COMPOSITE INTERPOSER STRUCTURE AND METHOD OF PROVIDING SAME
    3.
    发明申请
    COMPOSITE INTERPOSER STRUCTURE AND METHOD OF PROVIDING SAME 有权

    公开(公告)号：US20210159179A1

    公开(公告)日：2021-05-27

    申请号：US16698557

    申请日：2019-11-27

    Applicant: Intel Corporation

    Inventor： Adel Elsherbini ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast

    IPC: H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

    Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

    STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS
    7.
    发明申请
    STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS 有权

    公开(公告)号：US20220327083A1

    公开(公告)日：2022-10-13

    申请号：US17844366

    申请日：2022-06-20

    Applicant: Intel Corporation

    Inventor： Debendra Das Sharma ,  Swadesh Choudhary ,  Narasimha Lanka ,  Zuoguo Wu ,  Gerald Pasdast ,  Lakshmipriya Seshan

    IPC: G06F13/42 ,  H01L23/538 ,  G06F13/40

    Abstract: In one embodiment, a first die comprises: a first die-to-die adapter to communicate with first protocol layer circuitry via a flit-aware die-to-die interface (FDI) and first physical layer circuitry via a raw die-to-die interface (RDI), where the first die-to-die adapter is to receive message information comprising first information of a first interconnect protocol; and the first physical layer circuitry coupled to the first die-to-die adapter. The first physical layer circuitry may be configured to receive and output the first information to a second die via an interconnect, the first physical layer circuitry comprising a plurality of modules, each of the plurality of modules comprising an analog front end having transmitter circuitry and receiver circuitry. Other embodiments are described and claimed.

    DUAL LOOP VOLTAGE REGULATOR
    8.
    发明申请
    DUAL LOOP VOLTAGE REGULATOR 有权

    公开(公告)号：US20220197321A1

    公开(公告)日：2022-06-23

    申请号：US17128073

    申请日：2020-12-19

    Applicant: Intel Corporation

    Inventor： Sathya Narasimman Tiagaraj ,  Gerald Pasdast ,  Edward Burton

    IPC: G05F1/575 ,  G06F1/26

    Abstract: A dual-loop low-drop (LDO) regulator having a first loop which is an analog loop that compares the voltage on the output supply node with a reference, and generates a bias or voltage control to control a strength of a final power switch. The first loop regulates the output voltage relative to a reference voltage by minimizing the error between the two voltages. A second loop (digital loop) that controls a current source which injects current on the gate of the final power switch to boost current for a load. The second loop is an auxiliary loop that boosts the current load for a set interval until the tracking bandwidth of the LDO resolves the error in the output, thereby reducing the peak-to-peak noise. The quiescent current is not increased a lot by the second loop since the second loop circuit is on for a fraction of the entire LDO operation.

Patent Agency Ranking