公开(公告)号：US20190362772A1

公开(公告)日：2019-11-28

申请号：US16435878

申请日：2019-06-10

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Iqbal R. Rajwani ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Altug Koker ,  Abhisek R. Appu

IPC: G11C11/4094 ,  G06F9/38 ,  G11C11/4074 ,  G06F12/08 ,  G06F12/109 ,  G06F12/1027 ,  G06F12/0897 ,  G06F12/0868 ,  G06F13/40 ,  G06F3/06 ,  G06F9/30 ,  G11C11/4093

Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

公开(公告)号：US10324721B2

公开(公告)日：2019-06-18

申请号：US15488947

申请日：2017-04-17

Applicant: Intel Corporation

Inventor： Anupama A. Thaploo ,  Bhushan M. Borole ,  Bee Ngo ,  Iqbal R. Rajwani ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: G11C11/00 ,  G06F9/30 ,  G11C17/18 ,  G11C17/16 ,  G06F13/40 ,  G11C11/4094 ,  G11C7/12

Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.

公开(公告)号：US09947388B2

公开(公告)日：2018-04-17

申请号：US15072278

申请日：2016-03-16

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Iqbal R. Rajwani ,  Eric K. Donkoh

IPC: G11C7/22 ,  G11C11/419

CPC classification number: G11C11/419

Abstract: Described is an apparatus which comprises: a bit-line (BL) read port; a first local bit-line (LBL) coupled to the BL read port; a second LBL; and one or more clipper devices coupled to the first and second LBLs. The apparatus allows for low swing bit-line to be used for large signal memory arrays. The low swing operation enables reduction in switching dynamic capacitance. The apparatus also describes a split input NAND/NOR gate for bit-line keeper control which achieves lower VMIN, higher noise tolerance, and improved keeper aging mitigation. Described is also an apparatus for low swing write operation which can be enabled at high voltage without degrading the low voltage operation.

公开(公告)号：US11176990B2

公开(公告)日：2021-11-16

申请号：US17018071

申请日：2020-09-11

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Iqbal R. Rajwani ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Altug Koker ,  Abhishek R. Appu

IPC: G11C7/00 ,  G11C11/4094 ,  G06F9/30 ,  G06F12/0868 ,  G06F12/1027 ,  G11C11/4074 ,  G11C11/4093 ,  G06F13/40 ,  G06F9/38 ,  G11C11/419 ,  G06F12/0897 ,  G06F12/109 ,  G06F3/06 ,  G06F12/08

Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

公开(公告)号：US10817012B2

公开(公告)日：2020-10-27

申请号：US16527165

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Iqbal R. Rajwani ,  Altug Koker ,  Bhushan M. Borole ,  Kamal Sinha ,  Abhishek R. Appu ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Wenyin Fu

IPC: G06F1/06 ,  G06F1/08 ,  H03K19/09 ,  G06F9/38 ,  G06F13/16 ,  H03K19/096 ,  G06T1/60 ,  G06F9/30 ,  G06F1/14

Abstract: In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a register file having a plurality of entries, where at least a portion of the at least one graphics processor is to operate at a first operating frequency and the register file is to operate at a second operating frequency greater than the first operating frequency, to enable the at least one graphics processor to issue a plurality of write requests to the register file in a single clock cycle at the first operating frequency and receive a plurality of data elements of a plurality of read requests from the register file in the single clock cycle at the first operating frequency. Other embodiments are described and claimed.

公开(公告)号：US20190035452A1

公开(公告)日：2019-01-31

申请号：US16054207

申请日：2018-08-03

Applicant: Intel Corporation

Inventor： Bhushan M. Borole ,  Iqbal R. Rajwani ,  Anupama A. Thaploo ,  Sunil Nekkanti ,  Altug Koker ,  Abhisek R. Appu

IPC: G11C11/4094 ,  G06F3/06 ,  G11C11/4093 ,  G06F13/40 ,  G06F9/38 ,  G11C11/4074

CPC classification number: G11C11/4094 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/30123 ,  G06F9/30141 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3887 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/109 ,  G06F13/4068 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/419 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.

公开(公告)号：US20180062658A1

公开(公告)日：2018-03-01

申请号：US15244839

申请日：2016-08-23

Applicant: Intel Corporation

Inventor： Steven K. Hsu ,  Amit Agarwal ,  Iqbal R. Rajwani ,  Simeon Realov ,  Ram K. Krishnamurthy

IPC: H03K19/0944 ,  H03K19/20 ,  H03K19/00

CPC classification number: H03K19/0944 ,  H03K19/0013 ,  H03K19/20

Abstract: An apparatus is provided which comprises: a clock node; a test node; an enable node; and an AND-OR-INVERT (AOI) static latch coupled to the clock node, test node, and enable node, wherein the AOI static latch has embedded NOR functionality. Another apparatus comprises: a critical timing path having a pass-gate based integrated clock gate; and a non-critical timing path electrically coupled to the critical timing path, wherein the non-critical timing path includes an AND-OR-Inverter (AOI) based integrated clock gate with embedded NOR functionality.

公开(公告)号：US10754809B2

公开(公告)日：2020-08-25

申请号：US16354312

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Anupama A. Thaploo ,  Bhushan M. Borole ,  Bee Ngo ,  Iqbal R. Rajwani ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: G06F13/40 ,  G11C17/18 ,  G11C17/16 ,  G11C11/4094 ,  G06F9/30 ,  G11C7/12

Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.

公开(公告)号：US20190213161A1

公开(公告)日：2019-07-11

申请号：US16354312

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Anupama A. Thaploo ,  Bhushan M. Borole ,  Bee Ngo ,  Iqbal R. Rajwani ,  Altug Koker ,  Abhishek R. Appu ,  Kamal Sinha ,  Wenyin Fu

IPC: G06F13/40 ,  G06F9/30 ,  G11C17/18 ,  G11C11/4094 ,  G11C17/16

CPC classification number: G06F13/4068 ,  G06F9/30105 ,  G06F9/30141 ,  G06F13/4077 ,  G11C7/12 ,  G11C11/4094 ,  G11C17/16 ,  G11C17/18

Abstract: By shutting off keeper transistors during pre-charge, the aging on these devices may be reduced. This means that a relatively weaker keeper may be used for noise compared to an overdesigned stronger keeper. Using a relatively weaker keeper circuit results in a faster evaluation stage and improved minimum read voltage in some embodiments.

公开(公告)号：US10193536B2

公开(公告)日：2019-01-29

申请号：US15860562

申请日：2018-01-02

Applicant: INTEL CORPORATION

Inventor： Amit Agarwal ,  Steven K. Hsu ,  Simeon Realov ,  Iqbal R. Rajwani ,  Ram K. Krishnamurthy

IPC: H03K3/3562 ,  H03K3/037

Abstract: An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.