公开(公告)号：US12204901B2

公开(公告)日：2025-01-21

申请号：US17359305

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Robert Pawlowski ,  Sriram Aananthakrishnan ,  Jason Howard ,  Joshua Fryman

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

Abstract: Techniques for operating on an indirect memory access instruction, where the instruction accesses a memory location via at least one indirect address. A pipeline processes the instruction and a memory operation engine generates a first access to the at least one indirect address and a second access to a target address determined by the at least one indirect address. A cache memory used with the pipeline and the memory operation engine caches pointers. In response to a cache hit when executing the indirect memory access instruction, operations dereference a pointer to obtain the at least one indirect address, not set a cache bit, and return data for the instruction without storing the data in the cache memory; and in response to a cache miss, operations set the cache bit, obtain, and store a cache line for a missed pointer, and return data without storing the data in the cache memory.

公开(公告)号：US20230420411A1

公开(公告)日：2023-12-28

申请号：US17846153

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Omkar G. Karhade ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Nitin A. Deshpande ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L25/18 ,  H01L24/06 ,  H01L25/50 ,  H01L2224/80379 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/059 ,  H01L24/05 ,  H01L2224/05647 ,  H01L2224/05567 ,  H01L2224/06102 ,  H01L2224/06183 ,  H01L2224/08146 ,  H01L2224/08137 ,  H01L2224/0557 ,  H01L24/80 ,  H01L24/13 ,  H01L2224/13025 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/80006

Abstract: Embodiments of an integrated circuit (IC) die comprise: a metallization stack including a dielectric material, a plurality of layers of conductive traces in the dielectric material and conductive vias through the dielectric material; and a substrate attached to the metallization stack along a planar interface. The metallization stack comprises bond-pads on a first surface, a second surface, a third surface, a fourth surface, and a fifth surface. The first surface is parallel to the planar interface between the metallization stack and the substrate, the second surface is parallel to the third surface and orthogonal to the first surface, and the fourth surface is parallel to the fifth surface and orthogonal to the first surface and the second surface.

公开(公告)号：US20250160059A1

公开(公告)日：2025-05-15

申请号：US18508617

申请日：2023-11-14

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Joshua Fryman ,  Junyi Qiu ,  Mozhgan Mansuri ,  James Jaussi

IPC: H01L33/10 ,  H01L25/075 ,  H01L33/32 ,  H01L33/62

Abstract: A micro-LED includes a light emitter between a pair of reflective metasurfaces formed from nanostructures. The metasurfaces have different levels of reflectivity, with one metasurface reflecting nearly all light, and the other metasurface allowing some light to pass through. The reflections of the light within the micro-LED result in an improved radiation recombination rate, which results in an increased modulation speed. In addition, the light emitted from the micro-LED has a relatively narrow divergence angle and narrow emission linewidth, making the micro-LED suitable for optical communications.

公开(公告)号：US20240355980A1

公开(公告)日：2024-10-24

申请号：US18305525

申请日：2023-04-24

Applicant: Intel Corporation

Inventor： Daniel Klowden ,  Joshua Fryman

IPC: H01L33/62 ,  H01L33/58

CPC classification number: H01L33/62 ,  H01L33/58

Abstract: An IC package may include a stack of microelectronic units capable of horizontal and vertical optical communications. A microelectronic unit includes one or more power delivery pillars, two light source layers, an optical interconnect layer between the light source layers, and one or more IC devices arranged on the optical interconnect layer. A light source layer includes micro-LEDs that emit light used for generating optical signals. The optical interconnect layer includes one or more optical interconnects that enable horizontal optical communication, e.g., transmission of optical signals between the IC devices. A light source layer in the microelectronic unit can facilitate optical communications with another microelectronic unit that is below or above the microelectronic unit. A channel may exist above or below the light source layer to promote dissipation of heat generated by the IC devices. Light from the light source layer may pass through the channel for vertical optical communication.

公开(公告)号：US10983793B2

公开(公告)日：2021-04-20

申请号：US16369846

申请日：2019-03-29

Applicant: INTEL CORPORATION

Inventor： Joshua Fryman ,  Ankit More ,  Jason Howard ,  Robert Pawlowski ,  Yigit Demir ,  Nick Pepperling ,  Fabrizio Petrini ,  Sriram Aananthakrishnan ,  Shaden Smith

IPC: G06F9/30 ,  G06F13/28 ,  G06F9/32 ,  G06F9/455

Abstract: The present disclosure is directed to systems and methods of performing one or more broadcast or reduction operations using direct memory access (DMA) control circuitry. The DMA control circuitry executes a modified instruction set architecture (ISA) that facilitates the broadcast distribution of data to a plurality of destination addresses in system memory circuitry. The broadcast instruction may include broadcast of a single data value to each destination address. The broadcast instruction may include broadcast of a data array to each destination address. The DMA control circuitry may also execute a reduction instruction that facilitates the retrieval of data from a plurality of source addresses in system memory and performing one or more operations using the retrieved data. Since the DMA control circuitry, rather than the processor circuitry performs the broadcast and reduction operations, system speed and efficiency is beneficially enhanced.

公开(公告)号：US12158852B2

公开(公告)日：2024-12-03

申请号：US17358832

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Robert Pawlowski ,  Bharadwaj Krishnamurthy ,  Shruti Sharma ,  Byoungchan Oh ,  Jing Fang ,  Daniel Klowden ,  Jason Howard ,  Joshua Fryman

IPC: G06F13/28

Abstract: Systems, methods, and apparatuses for direct memory access instruction set architecture support for flexible dense compute using a reconfigurable spatial array are described. In one embodiment, a processor includes a first type of hardware processor core that includes a two-dimensional grid of compute circuits, a memory, and a direct memory access circuit coupled to the memory and the two-dimensional grid of compute circuits; and a second different type of hardware processor core that includes a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including a first field to identify a base address of two-dimensional data in the memory, a second field to identify a number of elements in each one-dimensional array of the two-dimensional data, a third field to identify a number of one-dimensional arrays of the two-dimensional data, a fourth field to identify an operation to be performed by the two-dimensional grid of compute circuits, and a fifth field to indicate the direct memory access circuit is to move the two-dimensional data indicated by the first field, the second field, and the third field into the two-dimensional grid of compute circuits and the two-dimensional grid of compute circuits is to perform the operation on the two-dimensional data according to the fourth field, and an execution circuit to execute the decoded single instruction according to the fields.

公开(公告)号：US20230420409A1

公开(公告)日：2023-12-28

申请号：US17846086

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Omkar G. Karhade ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Nitin A. Deshpande ,  Pushkar Sharad Ranade ,  Wilfred Gomes ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta ,  Michael Crocker ,  Aaron Gorius

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L23/5226 ,  H01L24/94 ,  H01L2224/80896 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L24/97

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; and a second region attached to the first region along a planar interface that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface. The first region comprises: a dielectric material; layers of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; conductive vias through the dielectric material; and bond-pads on the first surface, the bond-pads comprising portions of the conductive traces exposed on the first surface, and the second region comprises a material different from the dielectric material.

公开(公告)号：US11360809B2

公开(公告)日：2022-06-14

申请号：US16024343

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： William Paul Griffin ,  Joshua Fryman ,  Jason Howard ,  Sang Phill Park ,  Robert Pawlowski ,  Michael Abbott ,  Scott Cline ,  Samkit Jain ,  Ankit More ,  Vincent Cave ,  Fabrizio Petrini ,  Ivan Ganev

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30

Abstract: Embodiments of apparatuses, methods, and systems for scheduling tasks to hardware threads are described. In an embodiment, a processor includes a multiple hardware threads and a task manager. The task manager is to issue a task to a hardware thread. The task manager includes a hardware task queue to store a descriptor for the task. The descriptor is to include a field to store a value to indicate whether the task is a single task, a collection of iterative tasks, and a linked list of tasks.

公开(公告)号：US20220413855A1

公开(公告)日：2022-12-29

申请号：US17359305

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Robert Pawlowski ,  Sriram Aananthakrishnan ,  Jason Howard ,  Joshua Fryman

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

Abstract: Techniques for operating on an indirect memory access instruction, where the instruction accesses a memory location via at least one indirect address. A pipeline processes the instruction and a memory operation engine generates a first access to the at least one indirect address and a second access to a target address determined by the at least one indirect address. A cache memory used with the pipeline and the memory operation engine caches pointers. In response to a cache hit when executing the indirect memory access instruction, operations dereference a pointer to obtain the at least one indirect address, not set a cache bit, and return data for the instruction without storing the data in the cache memory; and in response to a cache miss, operations set the cache bit, obtain, and store a cache line for a missed pointer, and return data without storing the data in the cache memory.

公开(公告)号：US20200310795A1

公开(公告)日：2020-10-01

申请号：US16369846

申请日：2019-03-29

Applicant: INTEL CORPORATION

Inventor： Joshua Fryman ,  Ankit More ,  Jason Howard ,  Robert Pawlowski ,  Yigit Demir ,  Nick Pepperling ,  Fabrizio Petrini ,  Sriram Aananthakrishnan ,  Shaden Smith

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/455

Abstract: The present disclosure is directed to systems and methods of performing one or more broadcast or reduction operations using direct memory access (DMA) control circuitry. The DMA control circuitry executes a modified instruction set architecture (ISA) that facilitates the broadcast distribution of data to a plurality of destination addresses in system memory circuitry. The broadcast instruction may include broadcast of a single data value to each destination address. The broadcast instruction may include broadcast of a data array to each destination address. The DMA control circuitry may also execute a reduction instruction that facilitates the retrieval of data from a plurality of source addresses in system memory and performing one or more operations using the retrieved data. Since the DMA control circuitry, rather than the processor circuitry performs the broadcast and reduction operations, system speed and efficiency is beneficially enhanced.