公开(公告)号：US20170077389A1

公开(公告)日：2017-03-16

申请号：US15122911

申请日：2014-06-16

Applicant: INTEL CORPORATION

Inventor： Donald W. NELSON ,  M Clair WEBB ,  Patrick MORROW ,  Kimin JUN

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/02 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/522 ,  H01L23/5389 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L27/0694 ,  H01L27/101 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2924/00

Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein forming ones of the plurality of first interconnects and a plurality of second interconnects includes embedding memory devices therein. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein ones of the plurality of first interconnects and a plurality of second interconnects includes memory devices embedded therein.

Abstract translation: 一种方法，包括在包括多个电路装置的集成电路装置层的相对侧上形成多个第一互连和多个第二互连，其中形成多个第一互连中的一个和多个第二互连包括嵌入存储器件 其中。 一种装置，包括在包括多个电路装置的集成电路装置层的相对侧上包括多个第一互连和多个第二互连的基板，其中多个第一互连和多个第二互连中的一个包括存储装置 嵌入其中。

公开(公告)号：US20170069598A1

公开(公告)日：2017-03-09

申请号：US15122630

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： Donald W. NELSON ,  M Clair WEBB ,  Patrick MORROW ,  Kimin JUN

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/0652 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/06 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/1436 ,  H01L2924/00

Abstract: A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of second interconnects; coupling a second substrate including a memory device layer to the first substrate so that the memory device layer is juxtaposed to one of the plurality of first interconnects and the plurality of second interconnects; and removing a portion of the first substrate. An apparatus including a device layer including a plurality of circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate; a memory device layer including a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and contacts points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects.

Abstract translation: 一种包括形成第一衬底的方法，所述第一衬底包括设置在多个第一互连和多个第二互连之间的集成电路器件层; 将包括存储器件层的第二衬底耦合到所述第一衬底，使得所述存储器件层与所述多个第一互连和所述多个第二互连中的一个并置; 以及去除所述第一基板的一部分。 一种装置，包括：器件层，包括设置在基板上的多个第一互连和多个第二互连之间的多个电路器件; 存储器件层，包括并置并耦合到所述多个第一互连和所述多个第二互连中的一个的多个存储器件; 以及联接到所述第一多个互连中的一个和所述第二多个互连中的一个的接触点。