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    Power management in a bridge based on a second derivative value derived from a mathematical derivative of plurality of values corresponding to the received packets
    3.
    发明授权
    Power management in a bridge based on a second derivative value derived from a mathematical derivative of plurality of values corresponding to the received packets 有权
    基于从对应于接收到的分组的多个值的数学派生导出的二阶导数值，桥中的功率管理

    公开(公告)号：US09176554B2

    公开(公告)日：2015-11-03

    申请号：US13631868

    申请日：2012-09-29

    Applicant: Intel Corporation

    Inventor： Poh Thiam Teoh

    IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/266 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3253 ,  Y02D10/151

    Abstract: Methods and apparatus relating to robust governing of power management infrastructure in a bridge design are described. In one embodiment, a first agent (such as a processor core) is coupled to a second agent (such as an input/output device) via a bridge. The bridge may or may not enter a different power management state from a current power management state based on a second derivative value. The second derivative value may be in turn determined based on a plurality of first derivative values corresponding to received packets Other embodiments are also disclosed and claimed.

    Abstract translation: 描述了与桥梁设计中的电力管理基础设施的鲁棒控制有关的方法和设备。 在一个实施例中，第一代理（例如处理器核）经由桥耦合到第二代理（例如输入/输出设备）。 基于二阶导数值，桥接器可能或可能不从当前功率管理状态进入或不进入不同的功率管理状态。 也可以基于与接收到的分组对应的多个一阶导数值来确定二阶导数值。此外，还公开并要求保护其他实施方式。

    HARDWARE MECHANISMS FOR LINK ENCRYPTION
    5.
    发明申请
    HARDWARE MECHANISMS FOR LINK ENCRYPTION 审中-公开

    公开(公告)号：US20190229901A1

    公开(公告)日：2019-07-25

    申请号：US16368800

    申请日：2019-03-28

    Applicant: Intel Corporation

    Inventor： Reouven Elbaz ,  Hooi Kar Loo ,  Poh Thiam Teoh ,  Su Wei Lim ,  Patrick D. Maloney ,  Santosh Ghosh

    IPC: H04L9/08 ,  H04L9/12 ,  G06F13/42

    Abstract: Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.

    Link equalization mechanism
    8.
    发明授权
    Link equalization mechanism 有权
    链路均衡机制

    公开(公告)号：US09124455B1

    公开(公告)日：2015-09-01

    申请号：US14495768

    申请日：2014-09-24

    Applicant: INTEL CORPORATION

    Inventor： Su Wei Lim ,  Ronald W. Swartz ,  Yueming Jiang ,  Hooi Kar Loo ,  Athourina Gevergiz ,  Bruce A. Tennant ,  Yick Yaw Ho ,  Poh Thiam Teoh ,  Jennifer Chin ,  Hui Shi

    IPC: H03H7/30 ,  H04L25/03

    CPC classification number: H04L25/03885 ,  H04L25/03343 ,  H04L2025/03681

    Abstract: Techniques for embedded high speed serial interface methods are described herein. The techniques provide an apparatus for link equalization including an equalization control module to determine at least a first coefficient setting and a second coefficient setting at a remote transmitter based on an algorithm. The apparatus also includes a receiver margining module to determine a first margin value to be associated with the first coefficient setting and a second margin value to be associated with the second coefficient setting. The receiver margining module is to further determine if at least the first margin value is higher than the second margin value.

    Abstract translation: 本文描述了嵌入式高速串行接口方法的技术。 这些技术提供了一种用于链路均衡的装置，包括均衡控制模块，用于基于算法确定在远程发射机处的至少第一系数设置和第二系数设置。 该装置还包括接收器边界模块，用于确定与第一系数设置相关联的第一边距值和与第二系数设置相关联的第二边距值。 接收器余量模块用于进一步确定至少第一边际值是否高于第二边际值。

    Hardware mechanisms for link encryption
    9.
    发明授权
    Hardware mechanisms for link encryption 有权

    公开(公告)号：US11533170B2

    公开(公告)日：2022-12-20

    申请号：US16368800

    申请日：2019-03-28

    Applicant: Intel Corporation

    Inventor： Reouven Elbaz ,  Hooi Kar Loo ,  Poh Thiam Teoh ,  Su Wei Lim ,  Patrick D. Maloney ,  Santosh Ghosh

    IPC: H04L9/08 ,  G06F13/42 ,  H04L9/06 ,  H04L9/12 ,  H04L9/14

    Abstract: Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.

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