公开(公告)号：US20230130944A1

公开(公告)日：2023-04-27

申请号：US18089213

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Robert STARKSTON ,  Debendra MALLIK ,  John S. GUZEK ,  Chia-Pin CHIU ,  Deepak KULKARNI ,  Ravi V. MAHAJAN

IPC: H01L23/522 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20160268213A1

公开(公告)日：2016-09-15

申请号：US14642316

申请日：2015-03-09

Applicant: INTEL CORPORATION

Inventor： Hongjin JIANG ,  Robert STARKSTON ,  Digvijay A. RAORANE ,  Keith D. JONES ,  Ashish DHALL ,  Omkar G. KARHADE ,  Kedar DHANE ,  Suriyakala RAMALINGAM ,  Li-Sheng WENG ,  Robert F. CHENEY ,  Patrick N. STOVER

IPC: H01L23/552 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L23/16 ,  H01L23/49805 ,  H01L23/5383 ,  H01L23/562 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/32155 ,  H01L2224/73204 ,  H01L2224/83851 ,  H01L2924/014

Abstract: An apparatus including a package including a die and a package substrate, the package substrate including a conductor; and a stiffener body electrically coupled to the conductor of the package substrate. An apparatus including a package including a die and a package substrate; a stiffener body coupled to the package substrate; and an electrically conductive path between the stiffener body and the package substrate. A method including electrically coupling a stiffener body to a conductor of a package substrate.

Abstract translation: 一种包括包括管芯和封装基板的封装的装置，所述封装基板包括导体; 以及电耦合到封装衬底的导体的加强体。 一种包括包括管芯和封装衬底的封装的设备; 耦合到所述封装衬底的加强体; 以及在所述加强体和所述封装基板之间的导电路径。 一种包括将加强体电连接到封装基板的导体的方法。

公开(公告)号：US20160095209A1

公开(公告)日：2016-03-31

申请号：US14498958

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Robert STARKSTON ,  John GUZEK ,  Patrick NARDI ,  Keith JONES ,  Javier SOTO GONZALEZ

IPC: H05K1/02 ,  H01L23/498 ,  H05K1/18 ,  H01L21/48 ,  H05K1/11 ,  H01L23/31 ,  H01L23/00

CPC classification number: H05K1/0271 ,  H01L23/16 ,  H01L23/49833 ,  H01L23/562 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/284 ,  H05K2201/09136 ,  H05K2201/10977 ,  H05K2201/2009

Abstract: Techniques are disclosed for forming a package substrate with integrated stiffener. A panel of package substrates are provided. An adhesion layer is then formed on each package substrate of the panel of package substrates. A panel of stiffeners are then attached to the panel of package substrates by the adhesion layer, each stiffener corresponding to a respective package substrate. The panel of package substrates is then singulated into individual package substrates with integrated stiffeners. The stiffeners on the singulated package substrates include tabs that extend to the edges of the package substrates.

Abstract translation: 公开了用于形成具有集成的加强件的封装衬底的技术。 提供了一组封装基板。 然后在封装衬底面板的每个封装衬底上形成粘附层。 然后，通过粘合层将一块扶强材板附接到封装基板的面板，每个加强件对应于相应的封装基板。 然后将封装衬底的面板分成具有集成的加强件的单个封装衬底。 单个封装衬底上的加强件包括延伸到封装衬底的边缘的突片。

公开(公告)号：US20240421073A1

公开(公告)日：2024-12-19

申请号：US18818285

申请日：2024-08-28

Applicant: Intel Corporation

Inventor： Robert STARKSTON ,  Debendra MALLIK ,  John S. GUZEK ,  Chia-Pin CHIU ,  Deepak KULKARNI ,  Ravi V. MAHAJAN

IPC: H01L23/522 ,  H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US20230040850A1

公开(公告)日：2023-02-09

申请号：US17972340

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Robert STARKSTON ,  Debendra MALLIK ,  John S. GUZEK ,  Chia-Pin CHIU ,  Deepak KULKARNI ,  Ravi V. MAHAJAN

IPC: H01L23/522 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/538

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.