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    UNDERFILL MATERIAL FLOW CONTROL FOR REDUCED DIE-TO-DIE SPACING IN SEMICONDUCTOR PACKAGES
    3.
    发明申请
    UNDERFILL MATERIAL FLOW CONTROL FOR REDUCED DIE-TO-DIE SPACING IN SEMICONDUCTOR PACKAGES 审中-公开

    公开(公告)号：US20190148268A1

    公开(公告)日：2019-05-16

    申请号：US16228378

    申请日：2018-12-20

    Applicant: Intel Corporation

    Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Rajendra C. DIAS ,  Edvin CETEGEN ,  Lars D. SKOGLUND

    IPC: H01L23/485 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498 ,  H01L25/065

    Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

    LOW COST PACKAGE WARPAGE SOLUTION
    4.
    发明申请
    LOW COST PACKAGE WARPAGE SOLUTION 审中-公开

    公开(公告)号：US20200350181A1

    公开(公告)日：2020-11-05

    申请号：US16915290

    申请日：2020-06-29

    Applicant: Intel Corporation

    Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

    IPC: H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/16

    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

    LOW COST PACKAGE WARPAGE SOLUTION
    5.
    发明申请
    LOW COST PACKAGE WARPAGE SOLUTION 审中-公开

    公开(公告)号：US20190341271A1

    公开(公告)日：2019-11-07

    申请号：US16515981

    申请日：2019-07-18

    Applicant: Intel Corporation

    Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

    IPC: H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/16 ,  H01L25/18

    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

    LOW COST PACKAGE WARPAGE SOLUTION
    6.
    发明申请
    LOW COST PACKAGE WARPAGE SOLUTION 有权

    公开(公告)号：US20250096009A1

    公开(公告)日：2025-03-20

    申请号：US18961031

    申请日：2024-11-26

    Applicant: Intel Corporation

    Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

    IPC: H01L21/56 ,  H01L23/00 ,  H01L23/16 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

    LOW COST PACKAGE WARPAGE SOLUTION
    7.
    发明申请
    LOW COST PACKAGE WARPAGE SOLUTION 有权

    公开(公告)号：US20220230892A1

    公开(公告)日：2022-07-21

    申请号：US17715923

    申请日：2022-04-07

    Applicant: Intel Corporation

    Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

    IPC: H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/16

    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

    NOVEL METHOD AND MATERIALS FOR WARPAGE THERMAL AND INTERCONNECT SOLUTIONS
    8.
    发明申请
    NOVEL METHOD AND MATERIALS FOR WARPAGE THERMAL AND INTERCONNECT SOLUTIONS 审中-公开

    公开(公告)号：US20170200621A1

    公开(公告)日：2017-07-13

    申请号：US15469284

    申请日：2017-03-24

    Applicant: Intel Corporation

    Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE, JR. ,  Aditya Sundoctor VAIDYA ,  Nachiket R. RARAVIKAR ,  Eric J. LI

    IPC: H01L21/56 ,  H01L21/768 ,  H01L21/78

    Abstract: Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.

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