公开(公告)号：US20180190593A1

公开(公告)日：2018-07-05

申请号：US15396415

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Taylor GAINES ,  Anna M. PRAKASH ,  Suriyakala RAMALINGAM ,  Boxi LIU ,  Mohit GUPTA ,  Ziv BELMAN ,  Baruch SCHIFFMANN ,  Arnon HIRSHBERG ,  Vladimir MALAMUD ,  Ron WITTENBERG

IPC: H01L23/552 ,  H01L25/00 ,  H01L25/16 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L24/83 ,  H01L23/3142 ,  H01L23/552 ,  H01L24/27 ,  H01L24/32 ,  H01L25/167 ,  H01L25/50 ,  H01L31/107 ,  H01L2224/2731 ,  H01L2224/27318 ,  H01L2224/27418 ,  H01L2224/27505 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/83191 ,  H01L2224/8322 ,  H01L2224/8384 ,  H01L2224/83851 ,  H01L2924/0133 ,  H01L2924/0635 ,  H01L2924/0665 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1434 ,  H01L2924/3025

Abstract: In various embodiments this disclosure is directed to conductive adhesives layers that can be used, in one example embodiment, to connect one or more shielding structures (for example, metal cans and/or covers) to a semiconductor package to enclose one or more electronic components on the semiconductor package. In another embodiment, the conductive adhesive layers disclosed herein can be used in connection with optoelectronic devices (for example, optoelectronic devices including laser diodes and/or avalanche photodiodes, APDs). In one embodiment, the conductive adhesives can additionally be used for thermal dissipation and for electrical contact in connection with one or more electronic components on a semiconductor package. In one embodiment, various materials including, spray prints, conductive paste, inks (for example, sintering silver-based materials), epoxy material (for example, epoxy materials filled with silver and/or other metal particles) can be used to provide a conductive adhesive layer.

公开(公告)号：US20180342463A1

公开(公告)日：2018-11-29

申请号：US16035048

申请日：2018-07-13

Applicant: Intel Corporation

Inventor： Taylor GAINES ,  Anna M. PRAKASH ,  Suriyakala RAMALINGAM ,  Boxi LIU ,  Mohit GUPTA ,  Ziv BELMAN ,  Baruch SCHIFFMANN ,  Arnon HIRSHBERG ,  Vladimir MALAMUD ,  Ron WITTENBERG

IPC: H01L23/552 ,  H01L23/00 ,  H01L25/16 ,  H01L25/00 ,  H01L23/31 ,  H01L31/107 ,  H01S5/022

Abstract: In various embodiments this disclosure is directed to conductive adhesives layers that can be used, in one example embodiment, to connect one or more shielding structures (for example, metal cans and/or covers) to a semiconductor package to enclose one or more electronic components on the semiconductor package. In another embodiment, the conductive adhesive layers disclosed herein can be used in connection with optoelectronic devices (for example, optoelectronic devices including laser diodes and/or avalanche photodiodes, APDs). In one embodiment, the conductive adhesives can additionally be used for thermal dissipation and for electrical contact in connection with one or more electronic components on a semiconductor package. In one embodiment, various materials including, spray prints, conductive paste, inks (for example, sintering silver-based materials), epoxy material (for example, epoxy materials filled with silver and/or other metal particles) can be used to provide a conductive adhesive layer.

公开(公告)号：US20160268213A1

公开(公告)日：2016-09-15

申请号：US14642316

申请日：2015-03-09

Applicant: INTEL CORPORATION

Inventor： Hongjin JIANG ,  Robert STARKSTON ,  Digvijay A. RAORANE ,  Keith D. JONES ,  Ashish DHALL ,  Omkar G. KARHADE ,  Kedar DHANE ,  Suriyakala RAMALINGAM ,  Li-Sheng WENG ,  Robert F. CHENEY ,  Patrick N. STOVER

IPC: H01L23/552 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L23/16 ,  H01L23/49805 ,  H01L23/5383 ,  H01L23/562 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/32155 ,  H01L2224/73204 ,  H01L2224/83851 ,  H01L2924/014

Abstract: An apparatus including a package including a die and a package substrate, the package substrate including a conductor; and a stiffener body electrically coupled to the conductor of the package substrate. An apparatus including a package including a die and a package substrate; a stiffener body coupled to the package substrate; and an electrically conductive path between the stiffener body and the package substrate. A method including electrically coupling a stiffener body to a conductor of a package substrate.

Abstract translation: 一种包括包括管芯和封装基板的封装的装置，所述封装基板包括导体; 以及电耦合到封装衬底的导体的加强体。 一种包括包括管芯和封装衬底的封装的设备; 耦合到所述封装衬底的加强体; 以及在所述加强体和所述封装基板之间的导电路径。 一种包括将加强体电连接到封装基板的导体的方法。

公开(公告)号：US20240153837A1

公开(公告)日：2024-05-09

申请号：US17983226

申请日：2022-11-08

Applicant: Intel Corporation

Inventor： Ziyin LIN ,  Vipul MEHTA ,  Jonas CROISSANT ,  Jigneshkumar PATEL ,  Dingying XU ,  Gang DUAN ,  Aditya Sumanth YERRAMILLI ,  Suriyakala RAMALINGAM ,  Xavier BRUN

IPC: H01L23/31 ,  H01L23/498 ,  H01L25/18

CPC classification number: H01L23/3157 ,  H01L23/49811 ,  H01L25/18 ,  H01L24/32 ,  H01L2224/32225

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a die, and an array of pillars adjacent to the die. In an embodiment, the electronic package further comprises an underfill under the die, where an edge of the underfill is between an inner column of pillars in the array of pillars and an outer edge of the die, and where the edge of the underfill has a height that is less than a maximum height of the underfill.

公开(公告)号：US20180324955A1

公开(公告)日：2018-11-08

申请号：US15777893

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Mohit SOOD ,  Huili XU ,  Wei TAN ,  Suriyakala RAMALINGAM ,  Jan KRAJNIAK ,  Nish ANANTHAKRISHNAN

IPC: H05K3/34 ,  H01L23/498 ,  H05K3/40 ,  H05K3/12 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K3/3436 ,  H01L23/12 ,  H01L23/48 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/81024 ,  H01L2924/15311 ,  H05K1/111 ,  H05K1/181 ,  H05K3/1283 ,  H05K3/3494 ,  H05K3/4007 ,  H05K2201/10159 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/166 ,  Y02P70/613

Abstract: An apparatus is described. The apparatus includes a first planar board to second planar board interface. The first planar board to second planar board interface includes a reflowed solder electrical connection structure between the first and second boards and a no flow adhesive. The reflowed solder electrical connection structure includes a reflowed solder ball and a reflowed tinned pad.

公开(公告)号：US20180095503A1

公开(公告)日：2018-04-05

申请号：US15282950

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Sandeep S. IYER ,  Amanuel ABEBAW ,  Mark SALTAS ,  Mayank PATEL ,  Charavana K. GURUMURTHY ,  Suriyakala RAMALINGAM ,  Vladimir MALAMUD

IPC: G06F1/16 ,  H01F7/02

CPC classification number: G06F1/1684 ,  H01F7/0252

Abstract: An apparatus is provided which comprises: a chassis compartment having a bottom surface and walls orthogonal to the bottom, wherein the chassis compartment comprises: a rectangular opening, which may be designed to accept a microelectromechanical (MEMS) device and four slots, which may be designed to accept one or more magnet(s), extending outwardly from the rectangular opening, wherein each of the slots comprises: an inner opening having a length coextensive with a side of the rectangular opening, and an outer opening having corresponding ends that extend a length of the outer opening beyond the length of the inner opening. Other embodiments are also disclosed and claimed.

公开(公告)号：US20170186658A1

公开(公告)日：2017-06-29

申请号：US14998368

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Suriyakala RAMALINGAM ,  Yiqun BAI ,  Nisha ANANTHAKRISHNAN ,  Arjun KRISHNAN

IPC: H01L23/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/29 ,  H01L23/498

CPC classification number: H01L21/4853 ,  H01L23/15 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: Techniques and mechanisms for mitigating warpage of structures in a package. In an embodiment, a packaged integrated circuit device includes a mold compound disposed at least partially around an integrated circuit chip. The mold compound comprises fibers suspended in a media that is to aid in mechanical reinforcement of such fibers. The reinforced fibers contribute to mold compound properties that resist warping of the IC chip that might otherwise take place as a result of solder reflow or other processing. A modulus of elasticity of the mold compound is equal to or more than three GigePascals (3 GPa), where the modulus of elasticity corresponds to a temperature equal to two hundred and sixty degrees Celsius (260° C.). In another embodiment, a spiral flow value of the mold compound is equal to or more than sixty five centimeters (65 cm).