公开(公告)号：US09330039B2

公开(公告)日：2016-05-03

申请号：US13726748

申请日：2012-12-26

Applicant: INTEL CORPORATION

Inventor： Stephen H. Hall ,  Chaitanya Sreerama ,  Jason A. Mix ,  Michael W. Leddige ,  Jose A. Sanchez Sanchez ,  Olufemi B. Oluwafemi ,  Paul G. Huray ,  Maynard C. Falconer

IPC: G06F13/40

CPC classification number: G06F13/4022

Abstract: Techniques for encoding data are described herein. An example of a device in accordance with the present techniques includes a signaling module coupled to a plurality of digital inputs. The signaling module is to encode data received at the plurality of digital inputs to generate encoded data. Based on the encoded data, the signaling module can drive line voltages on a plurality of signal lines of a bus. Each one of the plurality of line voltages corresponds to a weighted sum of the data received at the plurality of digital inputs.

Abstract translation: 本文描述了用于编码数据的技术。 根据本技术的设备的示例包括耦合到多个数字输入的信令模块。 信令模块是对在多个数字输入端接收的数据进行编码，以生成编码数据。 基于编码数据，信令模块可以驱动总线的多个信号线上的线路电压。 多个线路电压中的每一个对应于在多个数字输入端接收的数据的加权和。

公开(公告)号：US09632961B2

公开(公告)日：2017-04-25

申请号：US13844671

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Olufemi B. Oluwafemi ,  Stephen H. Hall ,  Jason A. Mix ,  Earl J. Wight ,  Chaitanya Sreerama ,  Michael W. Leddige ,  Paul G. Huray

IPC: G06F13/40

CPC classification number: G06F13/4004 ,  G06F13/4022

Abstract: Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a receiving signaling module coupled to a plurality of signal lines. The signaling module includes a receiver to receive a plurality of encoded line voltages or currents on the plurality of signal lines of a bus, wherein each one of the plurality of encoded line voltages corresponds to a weighted sum of data. The signaling module includes a comparator to determine the voltage level of each line at a unit interval and convert the voltage level to a digital value. The signaling module includes a lookup table correlating the digital value with a digital bit stream.

公开(公告)号：US10652999B2

公开(公告)日：2020-05-12

申请号：US16327453

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Khang Choong Yong ,  Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Stephen H. Hall

IPC: H05K1/02

Abstract: Embodiments are generally directed to a mutual inductance suppressor for crosstalk immunity enhancement. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer, the second layer including a voltage reference plane; and a mutual inductance suppressor in the voltage reference plane, the mutual inductance suppressor including a serpentine portion of the voltage reference plane between the first signal trace and the second signal trace.

公开(公告)号：US10073807B2

公开(公告)日：2018-09-11

申请号：US14955043

申请日：2015-12-01

Applicant: Intel Corporation

Inventor： Chaitanya Sreerama ,  Stephen H. Hall

IPC: G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F15/78

CPC classification number: G06F13/4282 ,  G06F13/4022 ,  G06F13/4234 ,  G06F15/7817 ,  Y02D10/14 ,  Y02D10/151

Abstract: A logic-based decoder recovers binary data from ternary Crosstalk-Harnessed Signaling (CHS) streams with lower part cost, complexity and power consumption than analog/digital converter (ADC)-based CHS decoders. The decoders use inverters, latches, gates, latching circuits, and one comparator per bit pair to carry out the decoding calculations to produce a reconstructed binary signal with very low crosstalk noise that is largely insensitive to routing density. System-on-chip, multi-chip package, printed circuit board, and wired network applications are discussed.

公开(公告)号：US20170154007A1

公开(公告)日：2017-06-01

申请号：US14955043

申请日：2015-12-01

Applicant: Intel Corporation

Inventor： Chaitanya Sreerama ,  Stephen H. Hall

IPC: G06F13/42 ,  G06F15/78 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F13/4022 ,  G06F13/4234 ,  G06F15/7817 ,  Y02D10/14 ,  Y02D10/151

Abstract: A logic-based decoder recovers binary data from ternary Crosstalk-Harnessed Signaling (CHS) streams with lower part cost, complexity and power consumption than analog/digital converter (ADC)-based CHS decoders. The decoders use inverters, latches, gates, latching circuits, and one comparator per bit pair to carry out the decoding calculations to produce a reconstructed binary signal with very low crosstalk noise that is largely insensitive to routing density. System-on-chip, multi-chip package, printed circuit board, and wired network applications are discussed.

公开(公告)号：US09552995B2

公开(公告)日：2017-01-24

申请号：US14555124

申请日：2014-11-26

Applicant: Intel Corporation

Inventor： Khang Choong Yong ,  Bok Eng Cheah ,  Teong Keat Beh ,  Howard L. Heck ,  Jackson Chung Peng Kong ,  Stephen H. Hall ,  Kooi Chi Ooi

IPC: H01L23/498 ,  H01L21/288 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/2885 ,  H01L21/76802 ,  H01L21/76879 ,  H01L23/48 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/13 ,  H01L2224/1302 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a trench formed into one surface of the dielectric layer and a signal conductor that fills the trench and extends above the one surface of dielectric layer. The electrical interconnect further includes a conductive reference layer mounted on an opposing side of the dielectric layer. The conductive reference layer is electromagnetically coupled to the signal conductor when current passes through the signal conductor.

Abstract translation: 一些示例形式涉及电子封装的电互连。 电互连包括介电层，其包括形成在电介质层的一个表面中的沟槽和填充沟槽并在电介质层的一个表面上方延伸的信号导体。 电互连还包括安装在电介质层的相对侧上的导电参考层。 当电流通过信号导体时，导电参考层与信号导体电磁耦合。

公开(公告)号：US11178768B2

公开(公告)日：2021-11-16

申请号：US15089303

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Khang Choong Yong ,  Stephen H. Hall ,  Tin Poay Chuah ,  Boon Ping Koh ,  Eng Huat Goh

IPC: H05K1/18 ,  H05K1/14 ,  H01L25/18 ,  G06K9/00 ,  H05K1/02 ,  H05K9/00 ,  H05K3/36

Abstract: Three-dimensional (3-D) volumetric board architectural design provides technical solutions to technical problems facing miniaturization of circuit boards. The 3-D volumetric architecture includes using more of the unused volume in the vertical dimension (e.g., Z-dimension) to increase the utilization of the total circuit board volume. The 3-D volumetric architecture is realized by mounting components on a first PCB and on a second PCB, and inverting and suspending the second PCB above the first PCB. The use of 3-D volumetric board architectural design further enables formation of a shielded FEMIE, providing shielding and improved volumetric use with little or no reduction in system performance or increase in system Z-height.

公开(公告)号：US10078612B2

公开(公告)日：2018-09-18

申请号：US14444616

申请日：2014-07-28

Applicant: INTEL CORPORATION

Inventor： Michael W. Leddige ,  Stephen H. Hall ,  Chaitanya Sreerama ,  Olufemi B. Oluwafemi ,  Antonio Zenteno Ramirez ,  Maynard C. Falconer

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/20

CPC classification number: G06F13/4221 ,  G06F13/20

Abstract: An apparatus is described herein. The apparatus includes a plurality of conductors, wherein at least one conductor is a common-mode conductor. The apparatus also includes an encoder to encode data to be transmitted on the plurality of conductors, wherein a data speed of the common-mode conductor is limited and a data speed of other conductors is maximized according to an encoding matrix.

公开(公告)号：US20160026597A1

公开(公告)日：2016-01-28

申请号：US14444616

申请日：2014-07-28

Applicant: INTEL CORPORATION

Inventor： Michael W. Leddige ,  Stephen H. Hall ,  Chaitanya Sreerama ,  Olufemi B. Oluwafemi ,  Antonio Zenteno Ramirez ,  Maynard C. Falconer

IPC: G06F13/42 ,  G06F13/20

CPC classification number: G06F13/4221 ,  G06F13/20

Abstract: An apparatus is described herein. The apparatus includes a plurality of conductors, wherein at least one conductor is a common-mode conductor. The apparatus also includes an encoder to encode data to be transmitted on the plurality of conductors, wherein a data speed of the common-mode conductor is limited and a data speed of other conductors is maximized according to an encoding matrix.

Abstract translation: 这里描述了一种装置。 该装置包括多个导体，其中至少一个导体是共模导体。 该装置还包括编码器，用于编码要在多个导体上传输的数据，其中共模导体的数据速度受到限制，并且其他导体的数据速度根据编码矩阵最大化。