公开(公告)号：US10884483B2

公开(公告)日：2021-01-05

申请号：US16130916

申请日：2018-09-13

Applicant: Intel Corporation

Inventor： Jawad Haj-Yihia ,  Eliezer Weissmann ,  Vijay S. R. Degalahal ,  Nadav Shulman ,  Tal Kuzi ,  Itay Franko ,  Amit Gur ,  Efraim Rotem

IPC: G06F1/00 ,  G06F1/3287 ,  G06F1/3234

Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.

公开(公告)号：US10761594B2

公开(公告)日：2020-09-01

申请号：US15623536

申请日：2017-06-15

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Asaf Rubinstein ,  Arik Gihon ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC: G06F1/32 ,  G06F1/26 ,  G06F1/3296 ,  G06F1/3228 ,  G06F1/324

Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

公开(公告)号：US20180164873A1

公开(公告)日：2018-06-14

申请号：US15374684

申请日：2016-12-09

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Doron Rajwan ,  Tal Kuzi ,  Dean Mulla ,  Ariel Szapiro ,  Nir Tell

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.

公开(公告)号：US20170285703A1

公开(公告)日：2017-10-05

申请号：US15623536

申请日：2017-06-15

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Asaf Rubinstein ,  Arik Gihon ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/3228 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

公开(公告)号：US20170090945A1

公开(公告)日：2017-03-30

申请号：US14866584

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Eliezer Weissmann ,  Yoni Aizik ,  Itai Feit ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC: G06F9/44 ,  G06F1/24

CPC classification number: G06F11/3024 ,  G01V11/002 ,  G06F1/3228 ,  G06F1/324 ,  G06F9/5094 ,  G06F11/3058 ,  G06F11/3409 ,  G06F11/3419 ,  G06F11/3452 ,  G06F11/348 ,  G06F2201/88

Abstract: Methods and apparatus relating to techniques for flexible and/or dynamic frequency-related telemetry are described. In an embodiment, logic, coupled to a processor, communicates information to a module. The communicated information includes a duration counter value corresponding to a duration in which an operating characteristic of the processor is controlled. Other embodiments are also disclosed and claimed.

公开(公告)号：US09541949B2

公开(公告)日：2017-01-10

申请号：US14492179

申请日：2014-09-22

Applicant: Intel Corporation

Inventor： Tal Kuzi ,  Nadav Shulman ,  Ofer J. Nathan ,  Ori Levy ,  Itai Feit

IPC: G06F1/14 ,  G06F11/16 ,  G06F9/50

CPC classification number: G06F1/14 ,  G06F9/50 ,  G06F11/1658 ,  G06F2201/835

Abstract: In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括用于存储处理器的时间戳计数的主计数器，以及多个核心，每个核心包括用于存储核心时间戳计数的核心计数器。 处理器还包括响应于核心中的去同步事件的同步逻辑：获得主计数器的值; 使用主计数器的值来启动第一核心计数器，其中第一核心计数器包括在第一核心中; 将第一核心计数器的同步数字与指示主计数器的同步数字的值的同步信号进行比较; 并且响应于所述同步数字与所述同步信号不匹配的确定，基于所述同步信号的等待时间值来调整所述第一核心计数器的第一数字子集。 描述和要求保护其他实施例。

公开(公告)号：US20160252952A1

公开(公告)日：2016-09-01

申请号：US14634777

申请日：2015-02-28

Applicant: Intel Corporation

Inventor： Israel Diamand ,  Asaf Rubinstein ,  Arik Gihon ,  Tal Kuzi ,  Tomer Ziv ,  Nadav Shulman

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/3228 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

Abstract: In an embodiment, a processor includes a first core and a power management agent (PMA), coupled to the first core, to include a static table that stores a list of operations, and a plurality of columns each to specify a corresponding flow that includes a corresponding subset of the operations. Execution of each flow is associated with a corresponding state of the first core. The PMA includes a control register (CR) that includes a plurality of storage elements to receive one of a first value and a second value. The processor includes execution logic, responsive to a command to place the first core into a first state, to execute an operation of a first flow when a corresponding storage element stores the first value and to refrain from execution of an operation of the first flow when the corresponding element stores the second value. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括耦合到第一核的第一核和电源管理代理（PMA），以包括存储操作列表的静态表，以及多个列，以指定包括 相应的操作子集。 每个流的执行与第一核的相应状态相关联。 PMA包括控制寄存器（CR），其包括多个存储元件以接收第一值和第二值中的一个。 处理器包括执行逻辑，响应于将第一核放入第一状态的命令，当对应的存储元件存储第一值时，执行第一流的操作，并且当第一流处于 相应的元素存储第二个值。 描述和要求保护其他实施例。

公开(公告)号：US10474216B2

公开(公告)日：2019-11-12

申请号：US14971302

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Dorit Shapira ,  Itai Feit ,  Nadav Shulman ,  Efraim (Efi) Rotem ,  Tal Kuzi ,  Eliezer Weissmann ,  Tomer Ziv ,  Nir Rosenzweig

IPC: G06F1/32 ,  G06F13/42 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296

Abstract: A method and apparatus for providing power state information using in-band signaling are described. In one embodiment, an integrated circuit (IC) device comprises a controller operable to receive a command from a platform control bus, the command requesting data that is unrelated to information about a power state in which the IC resides; and control logic operable to obtain data for inclusion in a response to the command, wherein the controller is operable to send the response over a bus, the response containing at least a portion of the data responsive to the command and containing power state information for the IC.

公开(公告)号：US10365707B2

公开(公告)日：2019-07-30

申请号：US15374684

申请日：2016-12-09

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Doron Rajwan ,  Tal Kuzi ,  Dean Mulla ,  Ariel Szapiro ,  Nir Tell

IPC: G06F1/32 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324

Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.

公开(公告)号：US10114448B2

公开(公告)日：2018-10-30

申请号：US14322185

申请日：2014-07-02

Applicant: Intel Corporation

Inventor： Jawad Haj-Yihia ,  Eliezer Weissmann ,  Vijay S R Degalahal ,  Nadav Shulman ,  Tal Kuzi ,  Itay Franko ,  Amit Gur ,  Efraim Rotem

IPC: G06F1/00 ,  G06F1/32

Abstract: Methods and apparatus relating to autonomous C state mechanism and computational engine alignment for improved processor power efficiency. are described. An embodiment determines whether a semiconductor package should enter a package C state based on energy consumption values for entry into and exit from the package C state, an amount of time the semiconductor package stayed in the package C state previously, and one or more breakeven time points between the various package C states. Another embodiment detects a delay by an imaging computational unit of a processor to enter a low power consumption state relative to one or more other computational units of the processor. The logic causes the imaging computational unit to enter the low power consumption state in response to detection of the delay. Other embodiments are also disclosed and claimed.