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公开(公告)号：US09502468B2
公开(公告)日：2016-11-22
申请号：US14199174
申请日：2014-03-06
Applicant: Infineon Technologies AG
Inventor： Robert Strenz , Robert Allinger
CPC classification number: H01L27/2436 , G11C13/0002 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2013/0073 , G11C2213/71 , G11C2213/78 , G11C2213/79 , H01L45/08 , H01L45/147 , H01L45/16
Abstract: A nonvolatile memory device having a first resistive element coupled between a common node and a bit line; a second resistive element coupled between the common node and a word line; and a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output, wherein the word line is orthogonal to the bit line.
Abstract translation: 一种具有耦合在公共节点和位线之间的第一电阻元件的非易失性存储器件; 耦合在公共节点和字线之间的第二电阻元件; 以及传输晶体管，其具有耦合到所述公共节点的栅极，耦合到参考电压的第一节点和耦合到输出的第二节点，其中所述字线与所述位线正交。
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公开(公告)号：US20150162318A1
公开(公告)日：2015-06-11
申请号：US14101370
申请日：2013-12-10
Applicant: Infineon Technologies AG
Inventor： Robert Allinger , Gottfried Beer , Juergen Hoegerl
CPC classification number: H01L25/18 , G01R31/2884 , H01L22/26 , H01L22/34 , H01L24/06 , H01L24/09 , H01L25/0657 , H01L25/50 , H01L27/0248 , H01L2224/0401 , H01L2224/04042 , H01L2224/05022 , H01L2224/05554 , H01L2224/05555 , H01L2224/0603 , H01L2224/06051 , H01L2224/06131 , H01L2224/06132 , H01L2224/06136 , H01L2224/13147 , H01L2224/16148 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2225/0651 , H01L2225/06513 , H01L2225/06596 , H01L2924/14 , H01L2924/14252 , H01L2924/14253 , H01L2924/1426 , H01L2924/1433 , H01L2924/1434 , H01L2924/1438 , H01L2924/15311 , H01L2924/00014
Abstract: In various embodiments, a chip for a chip package is provided. The chip may include a substrate and an integrated circuit over the substrate. The integrated circuit may include a test circuit, for example a built-in self-test circuit, and an operation circuit, the test circuit including one or more first driver stages each having a first driver performance and the operation circuit including one or more second driver stages each having a second driver performance which is different from the first driver performance, first contacts electrically coupled with the first driver stages, and second contacts electrically coupled with the second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode.
Abstract translation: 在各种实施例中，提供了用于芯片封装的芯片。 芯片可以包括衬底和衬底上的集成电路。 集成电路可以包括测试电路，例如内置的自检电路和操作电路，测试电路包括一个或多个第一驱动器级，每个具有第一驱动器性能，并且该操作电路包括一个或多个第二 驱动器级各自具有与第一驱动器性能不同的第二驱动器性能，第一触点与第一驱动级电耦合，以及与第二驱动级电耦合的第二触点，其中测试电路和第一触点被配置为提供 用于测试集成电路的测试模式，并且其中所述操作电路和所述第二触点被配置为提供与所述测试模式不同的所述集成电路的操作模式。
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公开(公告)号：US09887006B1
公开(公告)日：2018-02-06
申请号：US15332149
申请日：2016-10-24
Applicant: Infineon Technologies AG
Inventor： Robert Strenz , Robert Allinger
CPC classification number: G11C13/0069 , G11C13/0007 , G11C13/0026 , G11C13/003 , G11C13/004 , G11C2013/0071 , G11C2013/0073 , G11C2213/75 , G11C2213/78 , G11C2213/79 , H01L27/2436 , H01L27/2481 , H01L45/14
Abstract: A nonvolatile memory device having a first resistive element coupled between a common node and a bit line; a second resistive element coupled between the common node and a word line, wherein the first and second resistive elements are coupled between different metal layers; and a pass transistor having a gate coupled to the common node, a first node coupled to a reference voltage, and a second node coupled to an output, wherein the word line is orthogonal to the bit line.
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4.发明授权Method for applying magnetic shielding layer, method for manufacturing a die, die and system 有权施加磁屏蔽层的方法，制造模具，模具和系统的方法公开(公告)号：US09583444B2
公开(公告)日：2017-02-28
申请号：US13970651
申请日：2013-08-20
Applicant: Infineon Technologies AG
Inventor： Christian Peters , Robert Allinger , Klaus Knobloch , Snezana Jenei
IPC: H01L23/552 , H01L43/02 , H01L43/12
CPC classification number: H01L23/552 , H01L43/02 , H01L43/12 , H01L2924/0002 , H01L2924/3025 , Y10T156/12 , H01L2924/00
Abstract: A method for applying a magnetic shielding layer to a substrate is provided, wherein a first magnetic shielding layer is adhered to a first surface of the substrate. A first film layer is adhered to the first magnetic shielding layer and the first magnetic shielding layer is more adherent to the first surface than the film layer to the first magnetic shielding layer.
Abstract translation: 提供了一种将磁屏蔽层施加到基板上的方法，其中第一磁屏蔽层粘附到基板的第一表面。 第一膜层粘附到第一磁屏蔽层，第一磁屏蔽层比第一磁屏蔽层比膜层更贴附于第一表面。
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公开(公告)号：US09564403B2
公开(公告)日：2017-02-07
申请号：US14038959
申请日：2013-09-27
Applicant: Infineon Technologies AG
Inventor： Robert Allinger , Karl Hofmann , Klaus Knobloch , Robert Strenz
IPC: H01L27/22 , H01L23/552 , H01L43/12 , H01L43/02 , H01L43/08
CPC classification number: H01L23/552 , G11C11/161 , H01L27/222 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/12 , H01L2924/0002 , H01L2924/00
Abstract: A memory having an array of perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM) cells, wherein each cell has a magnetic layer stack. A magnetic shield disposed between the cells and having a minimum height of at least the height of the magnetic layer stacks.
Abstract translation: 具有垂直自旋转移转矩（STT）磁性随机存取存储器（MRAM）单元的阵列的存储器，其中每个单元具有磁层堆叠。 设置在单元之间并且具有至少高度为磁层的最小高度的磁屏蔽。
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Patent Agency Ranking
公开(公告)号：US09331059B2
公开(公告)日：2016-05-03
申请号：US14101370
申请日：2013-12-10
Applicant: Infineon Technologies AG
Inventor： Robert Allinger , Gottfried Beer , Juergen Hoegerl
CPC classification number: H01L25/18 , G01R31/2884 , H01L22/26 , H01L22/34 , H01L24/06 , H01L24/09 , H01L25/0657 , H01L25/50 , H01L27/0248 , H01L2224/0401 , H01L2224/04042 , H01L2224/05022 , H01L2224/05554 , H01L2224/05555 , H01L2224/0603 , H01L2224/06051 , H01L2224/06131 , H01L2224/06132 , H01L2224/06136 , H01L2224/13147 , H01L2224/16148 , H01L2224/48091 , H01L2224/48227 , H01L2224/73207 , H01L2225/0651 , H01L2225/06513 , H01L2225/06596 , H01L2924/14 , H01L2924/14252 , H01L2924/14253 , H01L2924/1426 , H01L2924/1433 , H01L2924/1434 , H01L2924/1438 , H01L2924/15311 , H01L2924/00014
Abstract: In various embodiments, a chip for a chip package is provided. The chip may include a substrate and an integrated circuit over the substrate. The integrated circuit may include a test circuit, for example a built-in self-test circuit, and an operation circuit, the test circuit including one or more first driver stages each having a first driver performance and the operation circuit including one or more second driver stages each having a second driver performance which is different from the first driver performance, first contacts electrically coupled with the first driver stages, and second contacts electrically coupled with the second driver stages, wherein the test circuit and the first contacts are configured to provide a test mode for testing the integrated circuit and wherein the operation circuit and the second contacts are configured to provide an operating mode of the integrated circuit being different from the test mode.
Abstract translation: 在各种实施例中，提供了用于芯片封装的芯片。 芯片可以包括衬底和衬底上的集成电路。 集成电路可以包括测试电路，例如内置的自检电路和操作电路，测试电路包括一个或多个第一驱动器级，每个具有第一驱动器性能，并且该操作电路包括一个或多个第二 驱动器级各自具有与第一驱动器性能不同的第二驱动器性能，第一触点与第一驱动级电耦合，以及与第二驱动级电耦合的第二触点，其中测试电路和第一触点被配置为提供 用于测试集成电路的测试模式，并且其中所述操作电路和所述第二触点被配置为提供与所述测试模式不同的所述集成电路的操作模式。
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公开(公告)号：US11314642B2
公开(公告)日：2022-04-26
申请号：US16058620
申请日：2018-08-08
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Robert Allinger , Robert Strenz
IPC: G06F12/02 , G06F12/0804 , G06F3/06 , G11C11/56 , G11C16/16
Abstract: A method for updating a memory, which comprises several blocks, wherein each of the several blocks comprises multi-level cells and is operable in an MLC-mode or in a SLC-mode, wherein each multi-level cell may store more than one bit, wherein the method includes for each block to be updated: (a) copying the content of the block to a buffer block; (b) erasing the block; (c) writing the content of the block from the buffer block and an updated content for this block to this block, utilizing the capability of the block to be operated in the MLC-mode; (d) copying the updated content of the block to the buffer block; (e) erasing the block; and (f) writing the updated content from the buffer block to the block, utilizing the capability of the block to be operated in the SLC-mode. Also, therefore is a corresponding device.
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公开(公告)号：US20190057031A1
公开(公告)日：2019-02-21
申请号：US16058620
申请日：2018-08-08
Applicant: Infineon Technologies AG
Inventor： Thomas Kern , Robert Allinger , Robert Strenz
IPC: G06F12/0804 , G06F12/02 , G06F3/06 , G11C11/56 , G11C16/16
Abstract: A method for updating a memory, which comprises several blocks, wherein each of the several blocks comprises multi-level cells and is operable in an MLC-mode or in a SLC-mode, wherein each multi-level cell may store more than one bit, wherein the method includes for each block to be updated: (a) copying the content of the block to a buffer block; (b) erasing the block; (c) writing the content of the block from the buffer block and an updated content for this block to this block, utilizing the capability of the block to be operated in the MLC-mode; (d) copying the updated content of the block to the buffer block; (e) erasing the block; and (f) writing the updated content from the buffer block to the block, utilizing the capability of the block to be operated in the SLC-mode. Also, therefore is a corresponding device.
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公开(公告)号：US20150091109A1
公开(公告)日：2015-04-02
申请号：US14038959
申请日：2013-09-27
Applicant: Infineon Technologies AG
Inventor： Robert Allinger , Karl Hofmann , Klaus Knobloch , Robert Strenz
IPC: H01L23/552 , H01L43/12 , H01L27/22
CPC classification number: H01L23/552 , G11C11/161 , H01L27/222 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/12 , H01L2924/0002 , H01L2924/00
Abstract: A memory having an array of perpendicular spin-transfer torque (STT) magnetic random access memory (MRAM) cells, wherein each cell has a magnetic layer stack. A magnetic shield disposed between the cells and having a minimum height of at least the height of the magnetic layer stacks.
Abstract translation: 具有垂直自旋转移转矩（STT）磁性随机存取存储器（MRAM）单元的阵列的存储器，其中每个单元具有磁层堆叠。 设置在单元之间并且具有至少高度为磁层的最小高度的磁屏蔽。
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10.发明申请Method for Applying Magnetic Shielding Layer, Method for Manufacturing a Die, Die and System 有权应用磁屏蔽层的方法，制造模具，模具和系统的方法公开(公告)号：US20150054102A1
公开(公告)日：2015-02-26
申请号：US13970651
申请日：2013-08-20
Applicant: Infineon Technologies AG
Inventor： Christian Peters , Robert Allinger , Klaus Knobloch , Snezana Jenei
IPC: H01L23/552 , H01L43/12 , H01L43/02
CPC classification number: H01L23/552 , H01L43/02 , H01L43/12 , H01L2924/0002 , H01L2924/3025 , Y10T156/12 , H01L2924/00
Abstract: A method for applying a magnetic shielding layer to a substrate is provided, wherein a first magnetic shielding layer is adhered to a first surface of the substrate. A first film layer is adhered to the first magnetic shielding layer and the first magnetic shielding layer is more adherent to the first surface than the film layer to the first magnetic shielding layer.
Abstract translation: 提供了一种将磁屏蔽层施加到基板上的方法，其中第一磁屏蔽层粘附到基板的第一表面。 第一膜层粘附到第一磁屏蔽层，第一磁屏蔽层比第一磁屏蔽层比膜层更贴附于第一表面。
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