公开(公告)号：US10438640B2

公开(公告)日：2019-10-08

申请号：US16052552

申请日：2018-08-01

Applicant: Intel Corporation

Inventor： Liqiong Wei ,  Fatih Hamzaoglu ,  Yih Wang ,  Nathaniel J. August ,  Blake C. Lin ,  Cyrille Dray

IPC: G11C11/16 ,  G11C29/02 ,  G11C13/00

Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

公开(公告)号：US10068628B2

公开(公告)日：2018-09-04

申请号：US14129277

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Liqiong Wei ,  Fatih Hamzaoglu ,  Yih Wang ,  Nathaniel J. August ,  Blake C. Lin ,  Cyrille Dray

IPC: G11C11/16 ,  G11C29/02 ,  G11C13/00

Abstract: Apparatuses for improving resistive memory energy efficiency are provided. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

公开(公告)号：US20150348623A1

公开(公告)日：2015-12-03

申请号：US14290623

申请日：2014-05-29

Applicant: Intel Corporation

Inventor： Blake Lin ,  Cyrille Dray ,  Ananda Roy ,  Liqiong Wei ,  Faith Hamzaoglu

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0057 ,  G11C2013/0066 ,  G11C2013/0078

Abstract: Described are apparatuses and methods for improving resistive memory energy efficiency and reliability. An apparatus may include a resistive memory cell coupled to a conductive line. The apparatus may further include a driver coupled to the conductive line to drive current for the resistive memory cell during a write operation. The resistance of the driver may be selectively increased for two or more time periods during the write operation for detecting a voltage change on the conductive line. The current for the write operation may be turned off when the voltage change is detected to improve resistive memory energy efficiency and reliability.

Abstract translation: 描述了用于提高电阻式存储器能量效率和可靠性的装置和方法。 一种装置可以包括耦合到导线的电阻式存储单元。 该装置还可以包括耦合到导线的驱动器，以在写操作期间驱动电阻性存储单元的电流。 在用于检测导线上的电压变化的写入操作期间，可以选择性地增加驱动器的电阻两个或更多个时间段。 当检测到电压变化以提高电阻性存储器的能量效率和可靠性时，用于写入操作的电流可以被关闭。

公开(公告)号：US20170018298A1

公开(公告)日：2017-01-19

申请号：US15280935

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

IPC: G11C11/16 ,  G06F3/06

CPC classification number: G11C11/1675 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.

Abstract translation: 描述了一种用于提高读写余量的装置。 该装置包括：源线; 第一个位线 一列电阻存储器单元，该列的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到第一位线; 以及与所述第一位线并联的第二位线，所述第二位线用于解耦所述电阻存储器单元的位线上的读取和写入操作。 还描述了一种装置，其包括：源线; 有位 一列电阻存储器单元，列中的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到位线; 以及耦合到位线和源极线的源极线写入驱动器，其中源极线写入驱动器沿着电阻存储器单元的列分布。

公开(公告)号：US09418761B2

公开(公告)日：2016-08-16

申请号：US14569573

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Umut Arslan ,  Cyrille Dray

IPC: G11C11/00 ,  G11C29/50 ,  G11C13/00 ,  G11C29/08

CPC classification number: G11C29/08 ,  G11C7/14 ,  G11C13/0033 ,  G11C13/0038 ,  G11C13/004 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006

Abstract: Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a SourceLine (SL) of the column of resistive memory cells. Described is also an apparatus comprising: a memory array having rows and columns of resistive memory cells; a leakage tracker to track leakage current of a column of resistive memory cells associated with the memory array; and a circuit, coupled to the leakage tracker, for adaptively boosting voltage on a SL of the column of resistive memory cells during read operation.

Abstract translation: 描述了一种包括泄漏跟踪器以跟踪电阻式存储器单元的列的泄漏的装置; 以及用于调整电阻存储单元列的源线（SL）上的电压的电路。 还描述了一种装置，包括：具有电阻存储器单元的行和列的存储器阵列; 泄漏跟踪器，用于跟踪与所述存储器阵列相关联的一列电阻式存储器单元的泄漏电流; 以及耦合到泄漏跟踪器的电路，用于在读取操作期间自适应地升高电阻存储器单元的列上的电压。

公开(公告)号：US09875783B2

公开(公告)日：2018-01-23

申请号：US15115455

申请日：2014-03-03

Applicant: Intel Corporation

Inventor： Cyrille Dray ,  Liqiong Wei

IPC: G11C8/08 ,  G11C11/16 ,  G11C11/408

CPC classification number: G11C11/1697 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/418 ,  G11C13/0028 ,  G11C16/08

Abstract: Described is a word-line driver which is operable to switch a voltage level of a word-line to one of: first power supply, second power supply, or third power supply wherein the voltage level of the second power supply is higher than the voltage level of the first power supply, and wherein transistors of the word-line driver have same gate oxide thicknesses.

公开(公告)号：US09865322B2

公开(公告)日：2018-01-09

申请号：US15280935

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

IPC: G11C11/16 ,  G06F3/06

CPC classification number: G11C11/1675 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.

公开(公告)号：US11024356B2

公开(公告)日：2021-06-01

申请号：US16565299

申请日：2019-09-09

Applicant: Intel Corporation

Inventor： Liqiong Wei ,  Fatih Hamzaoglu ,  Yih Wang ,  Nathaniel J. August ,  Blake C. Lin ,  Cyrille Dray

IPC: G11C11/16 ,  G11C13/00 ,  G11C29/02

Abstract: Described are apparatuses for improving resistive memory energy efficiency. An apparatus performs data-driven write to make use of asymmetric write switch energy between write0 and write1 operations. The apparatus comprises: a resistive memory cell coupled to a bit line and a select line; a first pass-gate coupled to the bit line; a second pass-gate coupled to the select line; and a multiplexer operable by input data, the multiplexer to provide a control signal to the first and second pass-gates or to write drivers according to logic level of the input data. An apparatus comprises circuit for performing read before write operation which avoids unnecessary writes with an initial low power read operation. An apparatus comprises circuit to perform self-controlled write operation which stops the write operation as soon as bit-cell flips. An apparatus comprises circuit for performing self-controlled read operation which stops read operation as soon as data is detected.

公开(公告)号：US20160172059A1

公开(公告)日：2016-06-16

申请号：US14569573

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Umut Arslan ,  Cyrille Dray

IPC: G11C29/50 ,  G11C29/08 ,  G11C13/00

CPC classification number: G11C29/08 ,  G11C7/14 ,  G11C13/0033 ,  G11C13/0038 ,  G11C13/004 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006

Abstract: Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a SourceLine (SL) of the column of resistive memory cells. Described is also an apparatus comprising: a memory array having rows and columns of resistive memory cells; a leakage tracker to track leakage current of a column of resistive memory cells associated with the memory array; and a circuit, coupled to the leakage tracker, for adaptively boosting voltage on a SL of the column of resistive memory cells during read operation.

Abstract translation: 描述了一种包括泄漏跟踪器以跟踪电阻式存储器单元的列的泄漏的装置; 以及用于调整电阻存储单元列的源线（SL）上的电压的电路。 还描述了一种装置，包括：具有电阻存储器单元的行和列的存储器阵列; 泄漏跟踪器，用于跟踪与所述存储器阵列相关联的一列电阻式存储器单元的泄漏电流; 以及耦合到泄漏跟踪器的电路，用于在读取操作期间自适应地升高电阻存储器单元的列上的电压。

公开(公告)号：US09286976B2

公开(公告)日：2016-03-15

申请号：US14290623

申请日：2014-05-29

Applicant: Intel Corporation

Inventor： Blake Lin ,  Cyrille Dray ,  Ananda Roy ,  Liqiong Wei ,  Fatih Hamzaoglu

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C11/1675 ,  G11C11/1677 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0057 ,  G11C2013/0066 ,  G11C2013/0078

Abstract: Described are apparatuses and methods for improving resistive memory energy efficiency and reliability. An apparatus may include a resistive memory cell coupled to a conductive line. The apparatus may further include a driver coupled to the conductive line to drive current for the resistive memory cell during a write operation. The resistance of the driver may be selectively increased for two or more time periods during the write operation for detecting a voltage change on the conductive line. The current for the write operation may be turned off when the voltage change is detected to improve resistive memory energy efficiency and reliability.

Abstract translation: 描述了用于提高电阻式存储器能量效率和可靠性的装置和方法。 一种装置可以包括耦合到导线的电阻式存储单元。 该装置还可以包括耦合到导线的驱动器，以在写操作期间驱动电阻性存储单元的电流。 在用于检测导线上的电压变化的写入操作期间，可以选择性地增加驱动器的电阻两个或更多个时间段。 当检测到电压变化以提高电阻性存储器的能量效率和可靠性时，用于写入操作的电流可以被关闭。