公开(公告)号：US12176292B2

公开(公告)日：2024-12-24

申请号：US18375867

申请日：2023-10-02

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US11798861B2

公开(公告)日：2023-10-24

申请号：US16504698

申请日：2019-07-08

Applicant: Intel Corporation

Inventor： Peng Li ,  Kelly P. Lofgreen ,  Manish Dubey ,  Bamidele Daniel Falola ,  Ken Hackenberg ,  Shenavia S. Howell ,  Sergio Antonio Chan Arguedas ,  Yongmei Liu ,  Deepak Goyal

IPC: H01L23/34 ,  H01L21/48 ,  H01L23/433 ,  H01L23/367

CPC classification number: H01L23/345 ,  H01L21/4871 ,  H01L23/367 ,  H01L23/433

Abstract: Embodiments may relate to a microelectronic package that includes a lid coupled with a package substrate such that a die is positioned between the lid and the package substrate. The lid may include a heating element that is to heat an area between the lid and the die. Other embodiments may be described or claimed.

公开(公告)号：US11545407B2

公开(公告)日：2023-01-03

申请号：US16244748

申请日：2019-01-10

Applicant: Intel Corporation

Inventor： Kumar Abhishek Singh ,  Omkar Karhade ,  Nitin Deshpande ,  Mitul Modi ,  Edvin Cetegen ,  Aastha Uppal ,  Debendra Mallik ,  Sanka Ganesan ,  Yiqun Bai ,  Jan Krajniak ,  Manish Dubey ,  Ravindranath Mahajan ,  Ram Viswanath ,  James C. Matayabas, Jr.

IPC: H01L23/10 ,  H01L23/34 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H01L21/48

Abstract: An integrated circuit package may be formed having at least one heat dissipation structure within the integrated circuit package itself. In one embodiment, the integrated circuit package may include a substrate; at least one integrated circuit device, wherein the at least one integrated circuit device is electrically attached to the substrate; a mold material on the substrate and adjacent to the at least one integrated circuit device; and at least one heat dissipation structure contacting the at least one integrated circuit, wherein the at least one heat dissipation structure is embedded either within the mold material or between the mold material and the substrate.

公开(公告)号：US11302643B2

公开(公告)日：2022-04-12

申请号：US16829396

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US20210391295A1

公开(公告)日：2021-12-16

申请号：US16902927

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Sairam Agraharam ,  Edvin Cetegen ,  Anurag Tripathi ,  Malavarayan Sankarasubramanian ,  Jan Krajniak ,  Manish Dubey ,  Jinhe Liu ,  Wei Li ,  Jingyi Huang

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20200006273A1

公开(公告)日：2020-01-02

申请号：US16022453

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Kousik Ganesan ,  Suddhasattwa Nad ,  Thomas Heaton ,  Sri Chaitra Jyotsna Chavali ,  Amruthavalli Pallavi Alur

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

Abstract: A microelectronic device is formed including two or more structures physically and electrically engaged with one another through coupling of conductive features on the two structures. The conductive features may be configured to be tolerant of bump thickness variation in either of the structures. Such bump thickness variation tolerance can result from a contact structure on a first structure including a protrusion configured to extend in the direction of the second structure and to engage a deformable material on that second structure.

公开(公告)号：US20160343591A1

公开(公告)日：2016-11-24

申请号：US15225678

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： Suriyakala Ramalingam ,  Manish Dubey ,  Hsin-Yu Li ,  Michelle S. Phen-Givoni ,  Hitesh Arora ,  Nisha Ananthakrishnan ,  Yiqun Bai ,  Yonghao Xiu ,  Rajendra C. Dias

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/29

Abstract: Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having an underfill layer with filler particles arranged in a generally random distribution pattern. In some embodiments, a generally random distribution pattern of filler particles may be obtained by reducing an electrostatic charge on one or more components of the IC package assembly, by applying a surface treatment to filler to reduce filler electrical charge, by applying an electric force against the filler particles of the underfill material in a direction opposite to a direction of gravitational force, by using an underfill material with a relatively low maximum filler particle size, and/or by snap curing the underfill layer at a relatively low temperature. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及用于具有以通常随机分布图案排列的填充颗粒的底部填充层的集成电路（IC）封装的技术和配置。 在一些实施例中，通过对IC封装组件的一个或多个部件上的静电电荷，通过对填料进行表面处理以减少填充剂电荷，可以通过施加电力来抵抗填料颗粒的大致随机分布图案 通过使用相对较低的最大填充剂粒度的底部填充材料和/或通过在相对低的温度下快速固化底部填充层，使底部填充材料的填料颗粒在与重力方向相反的方向上。 可以描述和/或要求保护其他实施例。

公开(公告)号：US11791274B2

公开(公告)日：2023-10-17

申请号：US16902777

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Manish Dubey ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Jinhe Liu ,  Sairam Agraharam ,  Mohit Bhatia ,  Edvin Cetegen

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L23/528 ,  H01L23/532 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/1703

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20230134770A1

公开(公告)日：2023-05-04

申请号：US18090795

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US11640942B2

公开(公告)日：2023-05-02

申请号：US17677130

申请日：2022-02-22

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.