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    FIRST AND SECOND DIFFERENTIAL INTERCONNECTS HAVING INTERLEAVED STUB TRACES
    2.
    发明申请
    FIRST AND SECOND DIFFERENTIAL INTERCONNECTS HAVING INTERLEAVED STUB TRACES 审中-公开
    第一个和第二个具有交互式跟踪的差异互连

    公开(公告)号：US20170033425A1

    公开(公告)日：2017-02-02

    申请号：US15195090

    申请日：2016-06-28

    Applicant: Intel Corporation

    Inventor： Ruihua Ding ,  Min Wang ,  Mo Liu

    IPC: H01P3/08 ,  H01P11/00 ,  H05K1/02

    CPC classification number: H05K1/0245 ,  H01P1/203 ,  H01P3/026 ,  H01P3/04 ,  H01P3/08 ,  H01P11/003 ,  H04B3/32 ,  H05K1/0216 ,  H05K1/0228 ,  H05K3/10 ,  H05K2201/09236 ,  H05K2201/09781 ,  Y10T29/49155

    Abstract: This disclosure relates generally to an electronic assembly and method having a first electrical connection point and a second electrical connection point and a differential interconnect coupling the first electrical connection point to the second electrical connection point, the differential interconnect including first and second transmission traces including a interior edges and a exterior edges opposite the interior edges, the second interior edge facing the first interior edge, and stub traces, each stub trace coupled to one of the first and second transmission traces and projecting from one of the first interior edge, the first exterior edge, the second interior edge, and the second exterior edge. A substantially equal number of stub traces project from the first exterior edge and the second exterior edge. At least twice as many stub traces project from the first and second exterior edges as project from the first and second interior edges.

    Abstract translation: 本公开总体上涉及一种具有第一电连接点和第二电连接点的电子组件和方法，以及将第一电连接点耦合到第二电连接点的差分互连，差动互连包括第一和第二传输迹线，包括 内部边缘和与内部边缘相对的外部边缘，面向第一内部边缘的第二内部边缘和短截线迹线，每个短截线迹线耦合到第一和第二传输轨迹中的一个并从第一内部边缘中的一个突出，第一内部边缘 外部边缘，第二内部边缘和第二外部边缘。 从第一外边缘和第二外边缘突出的基本相等数量的短截线迹。 从第一和第二内部边缘起，从第一和第二外部边缘突出的短截线迹线的至少两倍。

    APPARATUSES AND METHODS FOR BALANCED TRANSMITTAL OF DATA
    3.
    发明申请
    APPARATUSES AND METHODS FOR BALANCED TRANSMITTAL OF DATA 审中-公开
    数据平衡传输的装置和方法

    公开(公告)号：US20170052923A1

    公开(公告)日：2017-02-23

    申请号：US14830612

    申请日：2015-08-19

    Applicant: Intel Corporation

    Inventor： Min Wang

    IPC: G06F13/42 ,  G06F13/16

    CPC classification number: G06F13/42 ,  G06F13/16

    Abstract: Methods and apparatuses relating to balanced transmittal of data are described. In one embodiment, an apparatus includes an encoder to encode input data into at least one data group with each data group having an equal number of a first level signal and a second, lower level signal to transmit the at least one data group over single conductors in parallel, and a decoder to decode the at least one data group into output data. In another embodiment, a method includes encoding input data with an encoder into at least one data group with each data group having an equal number of a first level signal and a second, lower level signal to transmit the at least one data group over single conductors in parallel, and decoding the at least one data group into output data with a decoder.

    Abstract translation: 描述与平衡传送数据有关的方法和装置。 在一个实施例中，一种装置包括编码器，用于将输入数据编码成至少一个数据组，每个数据组具有相等数量的第一电平信号和第二低电平信号，以通过单个导体传输至少一个数据组 以及解码器，用于将至少一个数据组解码为输出数据。 在另一个实施例中，一种方法包括将具有编码器的输入数据编码到至少一个数据组中，每个数据组具有相等数量的第一电平信号和第二低电平信号，以通过单个导体发送所述至少一个数据组 并且使用解码器将至少一个数据组解码为输出数据。

    DIFFERENTIAL INTERCONNECT TOPOLOGY IN A SUBSTRATE WITH STAGGERED VIAS
    6.
    发明申请
    DIFFERENTIAL INTERCONNECT TOPOLOGY IN A SUBSTRATE WITH STAGGERED VIAS 有权
    具有分离VIAS的基底中的差异互连拓扑

    公开(公告)号：US20160172734A1

    公开(公告)日：2016-06-16

    申请号：US14570791

    申请日：2014-12-15

    Applicant: Intel Corporation

    Inventor： Min Wang ,  Russell N. Shryock

    IPC: H01P3/08

    CPC classification number: H05K1/0245 ,  H01P3/026 ,  H05K1/0251 ,  H05K1/116 ,  H05K2201/09636

    Abstract: An interconnect topology is disclosed that includes a plurality of interconnections, each of which is coupled together using a via, where at least two of the vias are staggered with respect to each other. In one embodiment, the interconnect topology comprises a substrate, multiple signal traces routed through the substrate on multiple layers, and a plurality of vias, where each via couples a pair of the signal traces to form an interconnection between different ones of the multiple layers, and where a pair of vias comprise a first via to carry a positive differential signal via and a second via to carry a negative differential signal that are coupled to signal traces to form a differential signal pair. The differential first and second vias are staggered with respect to each other.

    Abstract translation: 公开了一种互连拓扑，其包括多个互连，每个互连使用通孔耦合在一起，其中至少两个通孔相对于彼此交错。 在一个实施例中，互连拓扑包括衬底，通过多层上的衬底布线的多个信号迹线以及多个通孔，其中每个通孔耦合一对信号迹线以形成多个不同层之间的互连， 并且其中一对通孔包括第一通孔以承载正差分信号通路和第二通孔，以携带耦合到信号迹线的负差分信号以形成差分信号对。 差分第一和第二通孔相对于彼此交错。

    First and second differential interconnects having interleaved stub traces
    7.
    发明授权
    First and second differential interconnects having interleaved stub traces 有权
    第一和第二差分互连具有交错短截线

    公开(公告)号：US09386690B2

    公开(公告)日：2016-07-05

    申请号：US14228002

    申请日：2014-03-27

    Applicant: Intel Corporation

    Inventor： Ruihua Ding ,  Min Wang ,  Mo Liu

    IPC: H05K1/02 ,  H01P3/04 ,  H04B3/32 ,  H05K3/10 ,  H01P3/02 ,  H01P1/203

    CPC classification number: H05K1/0245 ,  H01P1/203 ,  H01P3/026 ,  H01P3/04 ,  H01P3/08 ,  H01P11/003 ,  H04B3/32 ,  H05K1/0216 ,  H05K1/0228 ,  H05K3/10 ,  H05K2201/09236 ,  H05K2201/09781 ,  Y10T29/49155

    Abstract: This disclosure relates generally to an electronic assembly and method having a first electrical connection point and a second electrical connection point and a differential interconnect coupling the first electrical connection point to the second electrical connection point, the differential interconnect including first and second transmission traces including a interior edges and a exterior edges opposite the interior edges, the second interior edge facing the first interior edge, and stub traces, each stub trace coupled to one of the first and second transmission traces and projecting from one of the first interior edge, the first exterior edge, the second interior edge, and the second exterior edge. A substantially equal number of stub traces project from the first exterior edge and the second exterior edge. At least twice as many stub traces project from the first and second exterior edges as project from the first and second interior edges.

    Abstract translation: 本公开总体上涉及一种具有第一电连接点和第二电连接点的电子组件和方法，以及将第一电连接点耦合到第二电连接点的差分互连，差动互连包括第一和第二传输迹线，包括 内部边缘和与内部边缘相对的外部边缘，面向第一内部边缘的第二内部边缘和短截线迹线，每个短截线迹线耦合到第一和第二传输轨迹中的一个并从第一内部边缘中的一个突出，第一内部边缘 外部边缘，第二内部边缘和第二外部边缘。 从第一外边缘和第二外边缘突出的基本相等数量的短截线迹。 从第一和第二内部边缘起，从第一和第二外部边缘突出的短截线迹线的至少两倍。

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