公开(公告)号：US20240162134A1

公开(公告)日：2024-05-16

申请号：US18418154

申请日：2024-01-19

Applicant: Intel Corporation

Inventor： Xiao LU ,  Jiongxin LU ,  Christopher COMBS ,  Alexander HUETTIS ,  John HARPER ,  Jieping ZHANG ,  Nachiket R. RARAVIKAR ,  Pramod MALATKAR ,  Steven A. KLEIN ,  Carl DEPPISCH ,  Mohit SOOD

IPC: H01L23/498 ,  B23K3/06 ,  H01L23/538

CPC classification number: H01L23/49833 ,  B23K3/0623 ,  H01L23/49822 ,  H01L23/4985 ,  H01L23/5387

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.

公开(公告)号：US20180324955A1

公开(公告)日：2018-11-08

申请号：US15777893

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Mohit SOOD ,  Huili XU ,  Wei TAN ,  Suriyakala RAMALINGAM ,  Jan KRAJNIAK ,  Nish ANANTHAKRISHNAN

IPC: H05K3/34 ,  H01L23/498 ,  H05K3/40 ,  H05K3/12 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K3/3436 ,  H01L23/12 ,  H01L23/48 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/81024 ,  H01L2924/15311 ,  H05K1/111 ,  H05K1/181 ,  H05K3/1283 ,  H05K3/3494 ,  H05K3/4007 ,  H05K2201/10159 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/166 ,  Y02P70/613

Abstract: An apparatus is described. The apparatus includes a first planar board to second planar board interface. The first planar board to second planar board interface includes a reflowed solder electrical connection structure between the first and second boards and a no flow adhesive. The reflowed solder electrical connection structure includes a reflowed solder ball and a reflowed tinned pad.

公开(公告)号：US20210082798A1

公开(公告)日：2021-03-18

申请号：US16575307

申请日：2019-09-18

Applicant: Intel Corporation

Inventor： Xiao LU ,  Jiongxin LU ,  Christopher COMBS ,  Alexander HUETTIS ,  John HARPER ,  Jieping ZHANG ,  Nachiket R. RARAVIKAR ,  Pramod MALATKAR ,  Steven A. KLEIN ,  Carl DEPPISCH ,  Mohit SOOD

IPC: H01L23/498 ,  B23K3/06 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate; a second substrate; and an array of interconnects electrically coupling the first substrate to the second substrate. In an embodiment, the array of interconnects comprises first interconnects, wherein the first interconnects have a first volume and a first material composition, and second interconnects, wherein the second interconnects have a second volume and a second material composition, and wherein the first volume is different than the second volume and/or the first material composition is different than the second material composition.