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1.发明申请APPARATUS AND METHOD TO PROVIDE A THERMAL PARAMETER REPORT FOR A MULTI-CHIP PACKAGE 审中-公开提供多芯片封装的热参数报告的装置和方法公开(公告)号：US20160179158A1
公开(公告)日：2016-06-23
申请号：US14852859
申请日：2015-09-14
Applicant: Intel Corporation
Inventor： Tessil Thomas , Robin A. Steinbrecher , Sandeep Ahuja , Michael Berktold , Timothy Y. Kam , Howard Chin , Phani Kumar Kandula , Krishnakanth V. Sistla
CPC classification number: G06F1/206 , G06F1/3206 , G06F1/324 , G06F1/3296 , G06F3/0412 , Y02D10/126 , Y02D10/16 , Y02D10/172
Abstract: In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括至少一个核心和电源管理逻辑。 电源管理逻辑用于从包括处理器的封装内的多个管芯接收温度数据，并且确定多个温度控制裕度的最小温度控制裕度。 每个温度控制余量将基于与管芯相关联的相应的热控制温度并且还基于与管芯相关联的相应的温度数据来确定。 电源管理逻辑还可以生成包含最小温度控制余量的热报告，并存储热报告。 描述和要求保护其他实施例。
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公开(公告)号：US20160077567A1
公开(公告)日：2016-03-17
申请号：US14948174
申请日：2015-11-20
Applicant: Intel Corporation
Inventor： Gururaj K. Shamanna , Stefan Rusu , Phani Kumar Kandula , Sankalan Prasad , Mandar R. Ranade , Narayanan Natarajan , Tessil Thomas
CPC classification number: G06F1/28 , G05F1/625 , G06F1/3275 , G06F1/3296 , Y02D10/14 , Y02D10/172
Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.
Abstract translation: 描述了一种处理器，包括：多个晶体管，其可操作以提供动态可调节的晶体管尺寸，所述多个晶体管的一端耦合到第一电源并在另一端耦合到第二电源; 耦合到所述第二电源的电路，所述第二电源向所述电路提供电力; 以及功率控制单元（PCU），用于监测第一电源的电平，并且动态地调整多个晶体管的晶体管尺寸，使得调节第二电源以保持电路的可操作性。
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公开(公告)号：US12253901B2
公开(公告)日：2025-03-18
申请号：US17490290
申请日：2021-09-30
Applicant: Intel Corporation
Inventor： Nikos Kaburlasos , Rodrigo De Oliveira Vivi , Phani Kumar Kandula , Marc Beuchat , Mark J. Luckeroth , Eric J. M. Moret , David N. Lombard , John Kelbert , Brad Bittel
IPC: G06F1/32 , G06F1/08 , G06F1/3228 , G06F1/3296
Abstract: Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured to: determine whether the processor is active or idle; determine whether the on-chip temperature of the processor exceeds a first threshold; based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second (higher) threshold.
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公开(公告)号：US20210223805A1
公开(公告)日：2021-07-22
申请号：US17133279
申请日：2020-12-23
Applicant: Intel Corporation
Inventor： Rodrigo De Oliveira Vivi , John Kelbert , David Lombard , Eric Moret , Mark Luckeroth , Brad Bittel , Phani Kumar Kandula
Abstract: Methods, apparatus, systems, and articles of manufacture to reduce thermal fluctuations in semiconductor processors are disclosed. An apparatus includes a temperature analyzer to determine a current temperature of a processor. The apparatus further includes a controller to provide an idle workload to the processor to execute in response to the current temperature falling below a setback temperature.
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公开(公告)号：US10048744B2
公开(公告)日：2018-08-14
申请号：US14554384
申请日：2014-11-26
Applicant: Intel Corporation
Inventor： Tessil Thomas , Phani Kumar Kandula , Ramamurthy Krithivas , Howard Chin , Ian M. Steiner , Vivek Garg
Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US09921630B2
公开(公告)日：2018-03-20
申请号：US14948174
申请日：2015-11-20
Applicant: Intel Corporation
Inventor： Gururaj K. Shamanna , Stefan Rusu , Phani Kumar Kandula , Sankalan Prasad , Mandar R. Ranade , Narayanan Natarajan , Tessil Thomas
CPC classification number: G06F1/28 , G05F1/625 , G06F1/3275 , G06F1/3296 , Y02D10/14 , Y02D10/172
Abstract: Described is a processor comprising: a plurality of transistors operable to provide dynamically adjustable transistor size, the plurality of transistors coupled at one end to a first power supply and coupled at another end to a second power supply; a circuit coupled to the second power supply, the second power supply to provide power to the circuit; and a power control unit (PCU) to monitor the level of the first power supply, and to dynamically adjust the transistor size of the plurality of transistors so that the second power supply is adjusted to keep the circuit operational.
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公开(公告)号：US20230101997A1
公开(公告)日：2023-03-30
申请号：US17490290
申请日：2021-09-30
Applicant: Intel Corporation
Inventor： Nikos Kaburlasos , Rodrigo De Oliveira Vivi , Phani Kumar Kandula , Marc Beuchat , Mark J. Luckeroth , Eric J.M. Moret , David N. Lombard , John Kelbert , Brad Bittel
IPC: G06F1/3296 , G06F1/3228 , G06F1/08
Abstract: Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured to: determine whether the processor is active or idle; determine whether the on-chip temperature of the processor exceeds a first threshold; based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second (higher) threshold.
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公开(公告)号：US20200301490A1
公开(公告)日：2020-09-24
申请号：US16898603
申请日：2020-06-11
Applicant: Intel Corporation
Inventor： Tessil Thomas , Robin A. Steinbrecher , Sandeep Ahuja , Michael Berktold , Timothy Y. Kam , Howard Chin , Phani Kumar Kandula , Krishnakanth V. Sistla
IPC: G06F1/20 , G06F1/3296 , G06F1/3206 , G06F1/324 , G06F3/041
Abstract: In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.
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公开(公告)号：US20190205042A1
公开(公告)日：2019-07-04
申请号：US15856780
申请日：2017-12-28
Applicant: Intel Corporation
Inventor： Phani Kumar Kandula , Bharat S. Pillilli , Suresh Chemudupati , Yi-Feng Liu
IPC: G06F3/06 , G06F9/4401
CPC classification number: G06F3/0619 , G06F3/0629 , G06F3/0647 , G06F3/0653 , G06F3/0685 , G06F9/4403
Abstract: An apparatus is provided which includes: a first storage to store one or more parameters, a second storage to store data, and a third storage. The apparatus may further include a first circuitry to detect a triggering event. The apparatus may further include a second circuitry to, in response to the triggering event, cause transfer of the data from the second storage to the third storage, while one or more components of the apparatus is to operate in accordance with the one or more parameters.
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公开(公告)号：US20180335831A1
公开(公告)日：2018-11-22
申请号：US16052375
申请日：2018-08-01
Applicant: Intel Corporation
Inventor： Tessil Thomas , Phani Kumar Kandula , Ramamurthy Krithivas , Howard Chin , Ian M. Steiner , Vivek Garg
CPC classification number: G06F1/3296 , G06F1/206 , G06F1/32 , G06F1/3206 , G06F1/324 , Y02D10/126 , Y02D10/16 , Y02D10/172
Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.
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