公开(公告)号：US09880932B2

公开(公告)日：2018-01-30

申请号：US15688209

申请日：2017-08-28

Applicant: Intel Corporation

Inventor： Sanjay K. Kumar ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor ,  Andrew V. Anderson

IPC: G06F12/00 ,  G06F13/00 ,  G06F12/0804 ,  G06F11/14

CPC classification number: G06F12/0804 ,  G06F9/467 ,  G06F11/07 ,  G06F11/073 ,  G06F11/0778 ,  G06F11/0793 ,  G06F11/14 ,  G06F11/1482 ,  G06F12/0868 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2212/1032 ,  G06F2212/608

Abstract: A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to flush dirty data from a volatile cache to a persistent memory upon commitment of a store associated with the FoC instruction. The memory management unit includes logic to, based upon a flush-on-fail (FoF) mode, skip execution of the flush-on-commit instruction and to flush the dirty data from the volatile cache upon a subsequent FoF operation.

公开(公告)号：US12045640B2

公开(公告)日：2024-07-23

申请号：US16909084

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Sanjay K. Kumar ,  Philip Lantz ,  Rajesh Sankaran ,  Narayan Ranganathan ,  Saurabh Gayen ,  David A. Koufaty ,  Utkarsh Y. Kakaiya

IPC: G06F9/455 ,  G06F9/34 ,  G06F9/48 ,  G06F12/10 ,  G06F12/109 ,  G06F12/14

CPC classification number: G06F9/45558 ,  G06F9/342 ,  G06F9/4875 ,  G06F12/10 ,  G06F12/109 ,  G06F12/1441 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F12/145 ,  G06F12/1475 ,  G06F12/1483 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/656 ,  G06F2212/657

Abstract: In one embodiment, a data mover accelerator is to receive, from a first agent having a first address space and a first process address space identifier (PASID) to identify the first address space, a first job descriptor comprising a second PASID selector to specify a second PASID to identify a second address space. In response to the first job descriptor, the data mover accelerator is to securely access the first address space and the second address space. Other embodiments are described and claimed.

公开(公告)号：US11513924B2

公开(公告)日：2022-11-29

申请号：US16211934

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Nrupal Jani ,  Manasi Deval ,  Anjali Singhai Jain ,  Parthasarathy Sarangam ,  Mitu Aggarwal ,  Neerav Parikh ,  Alexander H. Duyck ,  Kiran Patil ,  Rajesh M. Sankaran ,  Sanjay K. Kumar ,  Utkarsh Y. Kakaiya ,  Philip Lantz ,  Kun Tian

IPC: G06F9/455 ,  G06F11/20 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G06F15/173 ,  G06F9/48

Abstract: Examples may include a method of instantiating a virtual machine; instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device by receiving input data requesting assigned resources for the virtual device, allocating assigned resources to the virtual device based at least in part on the input data, and mapping a page location in an address space of the shared physical device for a selected one of the assigned resources to a page location in a memory-mapped input/output (MMIO) space of the virtual device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the MMIO space of the virtual device.

公开(公告)号：US12117910B2

公开(公告)日：2024-10-15

申请号：US17868596

申请日：2022-07-19

Applicant: Intel Corporation

Inventor： Nrupal Jani ,  Manasi Deval ,  Anjali Singhai Jain ,  Parthasarathy Sarangam ,  Mitu Aggarwal ,  Neerav Parikh ,  Alexander H. Duyck ,  Kiran Patil ,  Rajesh M. Sankaran ,  Sanjay K. Kumar ,  Utkarsh Y. Kakaiya ,  Philip Lantz ,  Kun Tian

IPC: G06F11/20 ,  G06F3/06 ,  G06F9/455 ,  G06F9/48 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F15/173

CPC classification number: G06F11/2023 ,  G06F3/0622 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/45558 ,  G06F9/4856 ,  G06F11/2007 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4282 ,  G06F15/17331 ,  G06F2009/45562 ,  G06F2009/4557 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2009/45595 ,  G06F2201/805 ,  G06F2201/815 ,  G06F2213/0026

Abstract: Examples may include a method of instantiating a virtual machine, instantiating a virtual device to transmit data to and receive data from assigned resources of a shared physical device; and assigning the virtual device to the virtual machine, the virtual machine to transmit data to and receive data from the physical device via the virtual device.

公开(公告)号：US11573870B2

公开(公告)日：2023-02-07

申请号：US16211924

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Manasi Deval ,  Nrupal Jani ,  Anjali Singhai Jain ,  Parthasarathy Sarangam ,  Mitu Aggarwal ,  Neerav Parikh ,  Kiran Patil ,  Rajesh M. Sankaran ,  Sanjay K. Kumar ,  Utkarsh Y. Kakaiya ,  Philip Lantz ,  Kun Tian

IPC: G06F11/20 ,  G06F9/455 ,  G06F13/42 ,  G06F9/48 ,  G06F13/40 ,  G06F15/173 ,  G06F3/06 ,  G06F13/16 ,  G06F9/50 ,  G06F21/60 ,  G06F9/54

Abstract: Examples may include a computing platform having a host driver to get a packet descriptor of a received packet stored in a receive queue and to modify the packet descriptor from a first format to a second format. The computing platform also includes a guest virtual machine including a guest driver coupled to the host driver, the guest driver to receive the modified packet descriptor and to read a packet buffer stored in the receive queue using the modified packet descriptor, the packet buffer corresponding to the packet descriptor.

公开(公告)号：US20180285276A1

公开(公告)日：2018-10-04

申请号：US15476126

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Sanjay K. Kumar ,  Dheeraj R. Subbareddy ,  Jeffrey R. Jackson

IPC: G06F12/0873 ,  G06F17/30

CPC classification number: G06F12/0873 ,  G06F12/0238 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/0871 ,  G06F16/172 ,  G06F21/55 ,  G06F21/76 ,  G06F2212/1041 ,  G06F2212/225 ,  G06F2212/283 ,  G06F2212/608

Abstract: In one embodiment, an apparatus comprises a memory to store executable instructions of an operating system and a processor to identify a request for data from an application; determine whether a persistent page cache stores a copy of the data, wherein the persistent page cache is directly addressable by the processor and is to cache data of a storage device that is not directly addressable by the processor; and access the data from the persistent page cache.

公开(公告)号：US11556437B2

公开(公告)日：2023-01-17

申请号：US16211950

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Mitu Aggarwal ,  Nrupal Jani ,  Manasi Deval ,  Kiran Patil ,  Parthasarathy Sarangam ,  Rajesh M. Sankaran ,  Sanjay K. Kumar ,  Utkarsh Y. Kakaiya ,  Philip Lantz ,  Kun Tian

IPC: G06F9/455 ,  G06F9/46 ,  G06F11/20 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G06F15/173 ,  G06F9/48

Abstract: Examples include a method of live migrating a virtual device by creating a virtual device in a virtual machine, creating first and second interfaces for the virtual device, transferring data over the first interface, detecting a disconnection of the virtual device from the virtual machine, switching data transfers for the virtual device from the first interface to the second interface, detecting a reconnection of the virtual device to the virtual machine, and switching data transfers for the virtual device from the second interface to the first interface.

公开(公告)号：US11474916B2

公开(公告)日：2022-10-18

申请号：US16211955

申请日：2018-12-06

Applicant: Intel Corporation

Inventor： Mitu Aggarwal ,  Nrupal Jani ,  Manasi Deval ,  Kiran Patil ,  Parthasarathy Sarangam ,  Rajesh M. Sankaran ,  Sanjay K. Kumar ,  Utkarsh Y. Kakaiya ,  Philip Lantz ,  Kun Tian

IPC: G06F11/00 ,  G06F11/20 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40 ,  G06F15/173 ,  G06F9/455 ,  G06F9/48

Abstract: Examples include a method of performing failover of in an I/O architecture by allocating a first set of resources, associated with a first port of a physical device, to a virtual device, allocating a second set of resources, associated with a second port of the physical device, to the virtual device, assigning the virtual device to a virtual machine, activating the first set of resources, and transferring data between the virtual machine and the first port using the virtual device and the first set of resources. The method further includes detecting an error in the first set of resources, deactivating the first set of resources and activating the second set of resources, and transferring data between the virtual machine and the second port using the virtual device and the second set of resources.

公开(公告)号：US11461099B2

公开(公告)日：2022-10-04

申请号：US16911441

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Rajesh Sankaran ,  Gilbert Neiger ,  Philip Lantz ,  Sanjay K. Kumar

IPC: G06F9/34 ,  G06F9/30 ,  G06F12/109

Abstract: In one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (PASID) table; and an execution circuit coupled to the first configuration register. The execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a PASID table handle from the command data, access a first entry of the PASID table using the pointer from the first configuration register and the PASID table handle to obtain a PASID value, insert the PASID value into the command data, and send the command data to a device coupled to the processor. Other embodiments are described and claimed.

公开(公告)号：US11907744B2

公开(公告)日：2024-02-20

申请号：US16911445

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Utkarsh Y. Kakaiya ,  Sanjay K. Kumar ,  Philip Lantz ,  Gilbert Neiger ,  Rajesh Sankaran ,  Vedvyas Shanbhogue

IPC: G06F9/455 ,  G06F9/30 ,  G06F9/50 ,  G06F9/54

CPC classification number: G06F9/45558 ,  G06F9/30098 ,  G06F9/5005 ,  G06F9/546 ,  G06F2009/4557 ,  G06F2009/45579

Abstract: In one embodiment, a processor comprises: a first configuration register to store quality of service (QoS) information for a process address space identifier (PASID) value associated with a first process; and an execution circuit coupled to the first configuration register, where the execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, insert the QoS information and the PASID value into the command data, and send a request comprising the command data to a device coupled to the processor, to enable the device to use the QoS information of a plurality of requests to manage sharing between a plurality of processes. Other embodiments are described and claimed.