公开(公告)号：US12288789B2

公开(公告)日：2025-04-29

申请号：US18408223

申请日：2024-01-09

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani ,  Kalyan Kolluru ,  Nathan Jack ,  Nicholas Thomson ,  Ayan Kar ,  Benjamin Orr

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

公开(公告)号：US20240290788A1

公开(公告)日：2024-08-29

申请号：US18175591

申请日：2023-02-28

Applicant: Intel Corporation

Inventor： Guowei Xu ,  Tao Chu ,  Chiao-Ti Huang ,  Robin Chao ,  David Towner ,  Orb Acton ,  Omair Saadat ,  Feng Zhang ,  Dax M. Crum ,  Yang Zhang ,  Biswajeet Guha ,  Oleg Golonzka ,  Anand S. Murthy

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

Abstract: A metal gate fabrication method for nanoribbon-based transistors and associated transistor arrangements, IC structures, and devices are disclosed. An example IC structure fabricated using metal gate fabrication method described herein may include a first stack of N-type nanoribbons, a second stack of P-type nanoribbons, a first gate region enclosing portions of the nanoribbons of the first stack and including an NWF material between adjacent nanoribbons of the first stack, and a second gate region enclosing portions of the nanoribbons of the second stack and including a PWF material between adjacent nanoribbons of the second stack, where the second gate region includes the PWF material at sidewalls of the nanoribbons of the second stack and further includes the NWF material so that the PWF material is between the sidewalls of the nanoribbons of the second stack and the NWF material.

公开(公告)号：US11984449B2

公开(公告)日：2024-05-14

申请号：US17968558

申请日：2022-10-18

Applicant: Intel Corporation

Inventor： Cory Bomberger ,  Anand Murthy ,  Stephen Cea ,  Biswajeet Guha ,  Anupama Bowonder ,  Tahir Ghani

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/267 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/267

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having channel structures with sub-fin dopant diffusion blocking layers are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. The lower fin portion includes a dopant diffusion blocking layer on a first semiconductor layer doped to a first conductivity type. The upper fin portion includes a portion of a second semiconductor layer, the second semiconductor layer on the dopant diffusion blocking layer. An isolation structure is along sidewalls of the lower fin portion. A gate stack is over a top of and along sidewalls of the upper fin portion, the gate stack having a first side opposite a second side. A first source or drain structure at the first side of the gate stack.

公开(公告)号：US11908856B2

公开(公告)日：2024-02-20

申请号：US16719257

申请日：2019-12-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani ,  Kalyan Kolluru ,  Nathan Jack ,  Nicholas Thomson ,  Ayan Kar ,  Benjamin Orr

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/785

Abstract: Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

公开(公告)号：US11715787B2

公开(公告)日：2023-08-01

申请号：US17514058

申请日：2021-10-29

Applicant: Intel Corporation

Inventor： Mark Armstrong ,  Biswajeet Guha ,  Jun Sung Kang ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/266 ,  H01L21/26506 ,  H01L21/30604 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/7853

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.

公开(公告)号：US11676965B2

公开(公告)日：2023-06-13

申请号：US16146219

申请日：2018-09-28

Applicant: INTEL CORPORATION

Inventor： Stephen M. Cea ,  Tahir Ghani ,  Anand S. Murthy ,  Biswajeet Guha

IPC: H01L27/092 ,  H01L29/51 ,  H01L29/165 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L21/308 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H03K19/20

CPC classification number: H01L27/0924 ,  H01L21/3086 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/517 ,  H01L29/6681 ,  H01L29/66545 ,  H01L29/785 ,  H03K19/20

Abstract: Fabrication techniques for NMOS and PMOS nanowires leveraging an isolated process flow for NMOS and PMOS nanowires facilitates independent (decoupled) tuning/variation of the respective geometries (i.e., sizing) and chemical composition of NMOS and PMOS nanowires existing in the same process. These independently tunable degrees of freedom are achieved due to fabrication techniques disclosed herein, which enable the ability to individually adjust the width of NMOS and PMOS nanowires as well as the general composition of the material forming these nanowires independently of one another. In the context of nanowire based semiconductors, in which NMOS and PMOS nanowires are incorporated as channel, drain and source regions respectively for NMOS and PMOS nanowire transistors, independent tuning of the NMOS and PMOS nanowires facilitates independent tuning of short-channel effects, gate drive, the width of the transistor dead space capacitance, strain and other performance related characteristics of associated NMOS and PMOS nanowire transistors.

公开(公告)号：US11450738B2

公开(公告)日：2022-09-20

申请号：US16832417

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Sean T. Ma ,  Anand S. Murthy ,  Glenn A. Glass ,  Biswajeet Guha

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/10

Abstract: Disclosed herein are source/drain regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a channel region including a first semiconductor wire and a second semiconductor wire; and a source/drain region proximate to the channel region, wherein the source/drain region includes a first semiconductor portion proximate to an end of the first semiconductor wire, the source/drain region includes a second semiconductor portion proximate to an end of the second semiconductor wire, and the source/drain region includes a contact metal at least partially between the first semiconductor portion and the second semiconductor portion.

公开(公告)号：US11430868B2

公开(公告)日：2022-08-30

申请号：US16020361

申请日：2018-06-27

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Biswajeet Guha ,  Anupama Bowonder ,  Anand S. Murthy ,  Tahir Ghani ,  Stephen M. Cea

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L21/74 ,  H01L29/66 ,  H01L29/20 ,  H01L29/161 ,  H01L29/16

Abstract: Integrated circuit structures including a buried etch-stop layer to help control transistor source/drain depth are provided herein. The buried etch-stop layer addresses the issue of the source/drain etch (or epi-undercut (EUC) etch) going below the bottom of the active height of the channel region, as such an issue can result in un-controlled sub-fin leakage that causes power consumption degradation and other undesired performance issues. The buried etch-stop layer is formed below the channel material, such as in the epitaxial stack that includes the channel material, and acts to slow the removal of material after the channel material has been removed when etching to form the source/drain trenches. In other words, the buried etch-stop layer includes different material from the channel material that can be etched, for at least one given etchant, at a relatively slower rate than the channel material to help control the source/drain trench depth.

公开(公告)号：US11367796B2

公开(公告)日：2022-06-21

申请号：US16134817

申请日：2018-09-18

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  Mauro J. Kobrinsky ,  Tahir Ghani

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06

Abstract: Gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. A first conductive contact structure is coupled to the first epitaxial source or drain structure. A second conductive contact structure is coupled to the second epitaxial source or drain structure. The second conductive contact structure is deeper along the fin than the first conductive contact structure.

公开(公告)号：US11205715B2

公开(公告)日：2021-12-21

申请号：US16632856

申请日：2017-08-21

Applicant: Intel Corporation

Inventor： Mark Armstrong ,  Biswajeet Guha ,  Jun Sung Kang ,  Bruce Beattie ,  Tahir Ghani

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A method comprising: forming a substrate; forming a first nanowire over the substrate; forming a second nanowire over the substrate; forming a gate over a portion of the first and second nanowires; implanting a dopant such that a region between the first and second nanowires under the gate does not receive the dopant while a region between the first and second nanowires away from the gate receives the dopant, wherein the dopant amorphize a material of the region between the first and second nanowires away from the gate; and isotopically etching of the region between the first and second nanowires away from the gate.