公开(公告)号：US09019636B2

公开(公告)日：2015-04-28

申请号：US12980261

申请日：2010-12-28

Applicant: Jing-En Luan ,  Junyong Chen

Inventor： Jing-En Luan ,  Junyong Chen

IPC: G02B7/02

CPC classification number: G02B7/023 ,  G02B7/025

Abstract: Lens alignment apparatuses, methods and optical devices are disclosed. In accordance with various embodiments, a lens alignment apparatus may include at least one lens element positioned in a lens body. A lens alignment interface coupled to the lens element may be configured to permit the lens element to be angularly deflected relative to an axis of symmetry of the lens body. In other embodiments, a method of improving the resolution of an optical device may include translating a lens along an optical axis to maximize resolution at a first location, and determining a resolution in a second location in the imaging plane. The resolution in the second location may be improved by angularly deflecting the lens, and the position of the lens may then be fixed.

Abstract translation: 公开了透镜对准装置，方法和光学装置。 根据各种实施例，透镜对准装置可以包括定位在透镜体中的至少一个透镜元件。 耦合到透镜元件的透镜对准接口可以被配置为允许透镜元件相对于透镜主体的对称轴线成角度地偏转。 在其他实施例中，改进光学装置的分辨率的方法可以包括沿着光轴平移透镜以使第一位置处的分辨率最大化，以及确定成像平面中的第二位置中的分辨率。 可以通过使透镜成角度地偏转来改善第二位置中的分辨率，然后可以固定透镜的位置。

公开(公告)号：US08890269B2

公开(公告)日：2014-11-18

申请号：US13485624

申请日：2012-05-31

Applicant: Jing-En Luan

Inventor： Jing-En Luan

IPC: H01L31/18 ,  H01L31/0232 ,  H01L27/146

CPC classification number: H01L27/14625 ,  H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer-level camera sensor package includes a semiconductor substrate with an optical sensor on a front surface. Through-silicon-vias (TSV) extend through the substrate and provide I/O contact with the sensor from the back side of the substrate. A glass cover is positioned over the front surface, and the cover and substrate are embedded in a molding compound layer (MCL), the front surface of the MCL lying coplanar with the front of the cover, and the back surface lying coplanar with the back of the substrate. Surface-mount devices, electromagnetic shielding, and through-wafer-connectors can be embedded in the MCL. A redistribution layer on the back surface of the MCL includes bottom contact pads for mounting the package, and conductive traces interconnecting the contact pads, TSVs, surface-mount devices, shielding, and through-wafer-connectors. Anisotropic conductive adhesive is positioned on the front of the MCL for physically and electrically attaching a lens array.

Abstract translation: 晶片级摄像机传感器封装包括在前表面上具有光学传感器的半导体衬底。 穿透硅通孔（TSV）延伸穿过衬底，并从衬底的背面提供与传感器的I / O接触。 玻璃盖被定位在前表面上，并且盖和基板被嵌入在模塑复合层（MCL）中，MCL的前表面与盖的前部共面，并且后表面与背面共面 的基底。 表面贴装器件，电磁屏蔽和贯通晶圆连接器可嵌入MCL。 MCL背面的再分配层包括用于安装封装的底部接触焊盘，以及将接触焊盘，TSV，表面贴装器件，屏蔽和贯穿晶片连接器互连的导电迹线。 各向异性导电粘合剂位于MCL的前部，用于物理和电连接透镜阵列。

公开(公告)号：US20120178213A1

公开(公告)日：2012-07-12

申请号：US13424610

申请日：2012-03-20

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L21/60

CPC classification number: H01L23/367 ,  H01L23/04 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.

Abstract translation: 芯片级封装（CSP）器件包括具有电耦合到多个焊球的半导体管芯的CSP。 具有内顶表面和一个或多个侧壁的罐体限定了一个室。 CSP容纳在腔室中，并连接到罐的内部顶部表面。 印刷电路板附接到焊球和一个或多个侧壁以提供对CSP和罐的支撑。 CSP可能是晶片级CSP。 罐可以由金属物质或非金属物质制成。 在跌落测试期间和热循环测试期间，罐可以为CSP提供应力消除。

公开(公告)号：US20110157452A1

公开(公告)日：2011-06-30

申请号：US12651304

申请日：2009-12-31

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H04N5/225 ,  H01L33/00 ,  H01L31/00

CPC classification number: H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An optical sensor package has a transparent substrate with a redistribution layer formed on a face thereof, which includes a window and a plurality of electrically conductive traces. A semiconductor substrate, including an optical sensor and a plurality of contact terminals on a face thereof, is positioned on the transparent substrate in a face-to-face arrangement, with the optical sensor directly opposite the window, and with each of the contact terminals electrically coupled to a respective one of the electrically conductive terminals. The transparent substrate has larger overall dimensions than the semiconductor substrate, so that one or more edges of the transparent substrate extend beyond the corresponding edges of the semiconductor substrate. A plurality of solder balls are positioned on the face of the transparent substrate, each in electrical contact with a respective one of the electrically conductive terminals. The solder balls and the semiconductor substrate are at least partially encapsulated in an encapsulating layer formed on the face of the transparent substrate, which has been planarized to expose upper portions of the solder balls, as contact pads of the optical sensor package.

Abstract translation: 光学传感器封装具有在其表面上形成有再分布层的透明衬底，其包括窗口和多个导电迹线。 包括光学传感器和其表面上的多个接触端子的半导体衬底以与光学传感器直接相对的窗口面对面布置在透明衬底上，并且每个接触端子 电耦合到相应的一个导电端子。 透明基板具有比半导体基板更大的总体尺寸，使得透明基板的一个或多个边缘延伸超过半导体基板的对应边缘。 多个焊球定位在透明基板的表面上，每个焊球与相应的导电端子电接触。 焊球和半导体衬底至少部分地封装在形成在透明衬底的已被平坦化以暴露焊球上部的表面上的封装层中，作为光学传感器封装的接触焊盘。

公开(公告)号：US20110018125A1

公开(公告)日：2011-01-27

申请号：US12507049

申请日：2009-07-21

Applicant: Kum-Weng Loo ,  Jing-En Luan

Inventor： Kum-Weng Loo ,  Jing-En Luan

IPC: H01L23/373 ,  H01L23/34

CPC classification number: H01L23/16 ,  H01L23/3121 ,  H01L23/36 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/16152 ,  H01L2924/19105

Abstract: A semiconductor package includes a substrate board and a semiconductor die attached to a top surface of that substrate board. A heat spreader is provided over the semiconductor die. A stiffening ring is positioned surrounding the semiconductor die, the stiffening ring being attached to the top surface of the substrate board and attached to a bottom surface of the plate portion of the heat spreader. Space is left on the board outside of the stiffening ring to support the installation of passive components to the substrate board. An external ring may be included, with that external ring being interconnected to the stiffening ring by a set of tie bars. Alternatively, the heat spreader includes an integrally formed peripheral sidewall portion.

Abstract translation: 半导体封装包括衬底板和附接到该衬底板的顶表面的半导体管芯。 散热器设置在半导体管芯上。 加强环定位在半导体模具周围，加强环附接到基板的顶表面并且附接到散热器的板部分的底表面。 空间留在加强环外部的板上，以支持将无源部件安装到基板上。 可以包括外部环，该外环通过一组连接杆与加强环相互连接。 或者，散热器包括整体形成的外围侧壁部分。

公开(公告)号：US09025339B2

公开(公告)日：2015-05-05

申请号：US13340345

申请日：2011-12-29

Applicant: Jing-En Luan ,  Hk Looi

Inventor： Jing-En Luan ,  Hk Looi

IPC: H05K7/06 ,  H05K3/30 ,  H05K3/32 ,  H05K3/34

CPC classification number: H05K3/305 ,  H05K3/321 ,  H05K3/3421 ,  H05K2201/09781 ,  H05K2201/09909 ,  Y02P70/613 ,  Y10T29/4913

Abstract: On a circuit substrate on which an adhesive is used to couple electronic or structural components to the substrate, an adhesive dam is positioned to prevent the adhesive from interfering with the operation of the circuit. A contact pad can be provided at a selected location and with a selected shape, and solder deposited on the pad, then reflowed to form the dam. The dam can be a structure soldered to a contact pad, or the dam can be supported at its ends by another structure of the device, so that, at the location where it functions to contain the adhesive, it is not attached to the substrate.

Abstract translation: 在其上使用粘合剂将电子或结构部件耦合到基板的电路基板上，设置粘合剂阻挡层以防止粘合剂干扰电路的操作。 可以在选定的位置提供接触垫并具有选定的形状，并将焊料沉积在垫上，然后回流以形成坝。 大坝可以是焊接到接触垫的结构，或者可以通过设备的另一种结构在其端部处支撑坝，使得在其用于容纳粘合剂的位置处，该坝不附着到基底。

公开(公告)号：US20130320471A1

公开(公告)日：2013-12-05

申请号：US13485624

申请日：2012-05-31

Applicant: Jing-En Luan

Inventor： Jing-En Luan

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L27/14625 ,  H01L27/14618 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wafer-level camera sensor package includes a semiconductor substrate with an optical sensor on a front surface. Through-silicon-vias (TSV) extend through the substrate and provide I/O contact with the sensor from the back side of the substrate. A glass cover is positioned over the front surface, and the cover and substrate are embedded in a molding compound layer (MCL), the front surface of the MCL lying coplanar with the front of the cover, and the back surface lying coplanar with the back of the substrate. Surface-mount devices, electromagnetic shielding, and through-wafer-connectors can be embedded in the MCL. A redistribution layer on the back surface of the MCL includes bottom contact pads for mounting the package, and conductive traces interconnecting the contact pads, TSVs, surface-mount devices, shielding, and through-wafer-connectors. Anisotropic conductive adhesive is positioned on the front of the MCL for physically and electrically attaching a lens array.

Abstract translation: 晶片级摄像机传感器封装包括在前表面上具有光学传感器的半导体衬底。 穿透硅通孔（TSV）延伸穿过衬底，并从衬底的背面提供与传感器的I / O接触。 玻璃盖被定位在前表面上，并且盖和基板被嵌入在模塑复合层（MCL）中，MCL的前表面与盖的前部共面，并且后表面与背面共面 的基底。 表面贴装器件，电磁屏蔽和贯通晶圆连接器可嵌入MCL。 MCL背面的再分配层包括用于安装封装的底部接触焊盘，以及将接触焊盘，TSV，表面贴装器件，屏蔽和贯穿晶片连接器互连的导电迹线。 各向异性导电粘合剂位于MCL的前部，用于物理和电连接透镜阵列。

公开(公告)号：US08013438B2

公开(公告)日：2011-09-06

申请号：US12507049

申请日：2009-07-21

Applicant: Jing-En Luan ,  Kum-Weng Loo

Inventor： Jing-En Luan ,  Kum-Weng Loo

IPC: H01L23/34

CPC classification number: H01L23/16 ,  H01L23/3121 ,  H01L23/36 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/16152 ,  H01L2924/19105

Abstract: A semiconductor package includes a substrate board and a semiconductor die attached to a top surface of that substrate board. A heat spreader is provided over the semiconductor die. A stiffening ring is positioned surrounding the semiconductor die, the stiffening ring being attached to the top surface of the substrate board and attached to a bottom surface of the plate portion of the heat spreader. Space is left on the board outside of the stiffening ring to support the installation of passive components to the substrate board. An external ring may be included, with that external ring being interconnected to the stiffening ring by a set of tie bars. Alternatively, the heat spreader includes an integrally formed peripheral sidewall portion.

Abstract translation: 半导体封装包括衬底板和附接到该衬底板的顶表面的半导体管芯。 散热器设置在半导体管芯上。 加强环定位在半导体模具周围，加强环附接到基板的顶表面并且附接到散热器的板部分的底表面。 空间留在加强环外部的板上，以支持将无源部件安装到基板上。 可以包括外部环，该外环通过一组连接杆与加强环相互连接。 或者，散热器包括整体形成的外围侧壁部分。

公开(公告)号：US08934052B2

公开(公告)日：2015-01-13

申请号：US12938235

申请日：2010-11-02

Applicant: Jing-En Luan

Inventor： Jing-En Luan

IPC: H04N5/225 ,  H01L31/0232 ,  H01L27/146

CPC classification number: H04N5/2257 ,  H01L27/14618 ,  H01L31/02325 ,  H01L2924/0002 ,  H04N5/2251 ,  Y10T29/49002 ,  H01L2924/00

Abstract: A low profile chip scale module and method of making of the same. The low profile chip scale module includes embedded SMD and integrated EM shielding. An adhesive layer is arranged on a substrate, e.g., chip carrier. Dies and SMDs are arranged on the adhesive layer. An etched frame and molding is attached to the substrate. Inputs/outputs (I/O) are formed and the substrate is coated with a dielectric material. Metal lines and connections among bond pads are formed and another layer of dielectric material is applied as a protective layer. The substrate is cut into various predetermined sizes and a lens is attached to form the chip scale module.

Abstract translation: 一种低调的芯片规模模块及其制造方法。 低调芯片尺寸模块包括嵌入式SMD和集成EM屏蔽。 粘合剂层布置在基底上，例如芯片载体上。 模具和SMD布置在粘合剂层上。 将蚀刻的框架和模制件附接到基板。 形成输入/输出（I / O），并且用电介质材料涂覆基板。 形成金属线和接合焊盘之间的连接，另外施加介电材料层作为保护层。 将基板切割成各种预定尺寸，并且连接透镜以形成芯片刻度模块。

公开(公告)号：US08884422B2

公开(公告)日：2014-11-11

申请号：US12651365

申请日：2009-12-31

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L23/04 ,  H01L29/40 ,  H01L25/10 ,  H01L23/498 ,  H01L21/56 ,  H01L25/16 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L21/565 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

Abstract: A flip-chip fan-out wafer level package for package-on-package applications includes a semiconductor die with solder bumps on an upper surface in a flip chip configuration. The die is inverted, with an upper surface facing an upper side of a redistribution layer, with the solder bumps in electrical contact with respective chip contact pads of the redistribution layer. The redistribution layer includes conductive traces that place each of the solder bumps in electrical contact with one or both of one of a plurality of upper redistribution contact pads and one of a plurality of lower redistribution contact pads. Each of the plurality of upper redistribution contact pads has an upper solder ball in electrical contact therewith. The die and the upper solder balls are at least partially encapsulated in a layer of mold compound positioned on the upper surface of the redistribution layer, and whose lateral dimensions are defined by the lateral dimensions of the redistribution layer. The layer of mold compound has a back-ground surface at which a portion of each of the upper solder balls is exposed, for electrical contact with an upper package. Each of the lower redistribution contact pads has a lower solder ball a coupled thereto.

Abstract translation: 用于封装封装应用的倒装芯片扇出晶片级封装包括在倒装芯片配置的上表面上具有焊料凸块的半导体管芯。 模具倒置，上表面面向再分布层的上侧，焊料凸块与再分布层的相应芯片接触焊盘电接触。 再分配层包括导电迹线，其将每个焊料凸点与多个上再分布接触焊盘和多个下再分布接触焊盘之一中的一个或两者电接触。 多个上再分配接触垫中的每一个具有与其接触的上焊球。 模具和上焊球至少部分地封装在位于再分配层的上表面上的模具化合物层中，并且其横向尺寸由再分布层的横向尺寸限定。 模具化合物层具有背面表面，每个上焊球的一部分暴露在其中，用于与上封装电接触。 每个下再分布接触垫具有与其耦合的较低焊球。