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    Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse
    1.
    发明授权
    Anti-fuse, anti-fuse circuit including the same, and method of fabricating the anti-fuse 有权
    防熔丝，反熔丝电路包括相同，以及制造防熔丝的方法

    公开(公告)号：US08514648B2

    公开(公告)日：2013-08-20

    申请号：US13051998

    申请日：2011-03-18

    申请人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    发明人： Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    IPC分类号： G11C17/18

    CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

    摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。

    ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE
    2.
    发明申请
    ANTI-FUSE, ANTI-FUSE CIRCUIT INCLUDING THE SAME, AND METHOD OF FABRICATING THE ANTI-FUSE 有权
    抗保险丝，包括其中的防熔丝电路以及制造防熔丝的方法

    公开(公告)号：US20110267915A1

    公开(公告)日：2011-11-03

    申请号：US13051998

    申请日：2011-03-18

    申请人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    发明人： Jong-Pil SON ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Doo-Young Kim ,  Hyoung-Joo Kim ,  Ju-Seop Park

    IPC分类号： G11C8/10 ,  H01L29/78 ,  H01L27/088

    CPC分类号： H01L23/5252 ,  G11C17/16 ,  G11C29/785 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are an anti-fuse, an anti-fuse circuit, and a method of fabricating the anti-fuse. The anti-fuse includes a semiconductor substrate, an isolation region, a channel diffusion region, a gate oxide layer, and a gate electrode. The semiconductor substrate includes a top surface and a bottom portion, the bottom portion of the semiconductor substrate having a first conductivity type. The isolation region is disposed inward from the top surface of the semiconductor substrate to a first depth. The channel diffusion region is disposed inward from the top surface of the semiconductor substrate to a second depth, the second depth located at a depth where the channel diffusion region meets an upper boundary of the bottom portion of the semiconductor substrate. The channel diffusion region is surrounded by the isolation region, the first depth is a greater distance from the top surface of the semiconductor substrate than the second depth, and the channel diffusion region has a second conductivity type opposite to the first conductivity type. The gate oxide layer is disposed on the channel diffusion region, and the gate electrode is disposed on the gate oxide layer to cover a top surface of the gate oxide layer.

    摘要翻译： 提供反熔丝，反熔丝电路和制造反熔丝的方法。 反熔丝包括半导体衬底，隔离区，沟道扩散区，栅极氧化层和栅电极。 半导体衬底包括顶表面和底部，半导体衬底的底部具有第一导电类型。 隔离区域从半导体衬底的顶表面向内设置到第一深度。 沟道扩散区域从半导体衬底的顶表面向内设置到第二深度，第二深度位于沟道扩散区域与半导体衬底的底部的上边界相交的深度处。 沟道扩散区域由隔离区域包围，第一深度比半导体衬底的顶表面的距离大于第二深度，并且沟道扩散区域具有与第一导电类型相反的第二导电类型。 栅极氧化层设置在沟道扩散区上，并且栅电极设置在栅极氧化层上以覆盖栅极氧化物层的顶表面。

    Fuse circuit and semiconductor memory device including the same
    5.
    发明授权
    Fuse circuit and semiconductor memory device including the same 有权
    保险丝电路和包括其的半导体存储器件

    公开(公告)号：US08599635B2

    公开(公告)日：2013-12-03

    申请号：US13205966

    申请日：2011-08-09

    申请人： Jin-Ho Kim ,  Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Seung-Hoon Oh ,  Ju-Seop Park

    发明人： Jin-Ho Kim ,  Jong-Pil Son ,  Seong-Jin Jang ,  Byung-Sik Moon ,  Seung-Hoon Oh ,  Ju-Seop Park

    IPC分类号： G11C17/18

    CPC分类号： G11C29/027 ,  G11C17/16 ,  G11C29/04

    摘要： A fuse circuit includes a program unit, a sensing unit and a control unit. The program unit is programmed in response to a program signal, and outputs a program output signal in response to a sensing enable signal. The sensing unit includes a variable resistor unit that has a resistance that varies based on a control signal, and generates a sensing output signal based on the resistance of the variable resistor unit and the program output signal. The control unit generates the control signal having a value changed depending on operation modes, and performs a verification operation with respect to the program unit based on the sensing output signal to generate a verification result. The program unit may be re-programmed based on the verification result.

    摘要翻译： 熔丝电路包括程序单元，感测单元和控制单元。 程序单元响应于程序信号被编程，并且响应于感测使能信号而输出程序输出信号。 感测单元包括具有基于控制信号而变化的电阻的可变电阻器单元，并且基于可变电阻器单元的电阻和程序输出信号产生感测输出信号。 控制单元产生具有根据操作模式改变的值的控制信号，并且基于感测输出信号执行关于节目单元的验证操作以产生验证结果。 程序单元可以基于验证结果重新编程。

    Redundancy program circuit and methods thereof
    9.
    发明授权
    Redundancy program circuit and methods thereof 有权
    冗余编程电路及其方法

    公开(公告)号：US07307910B2

    公开(公告)日：2007-12-11

    申请号：US11169831

    申请日：2005-06-30

    申请人： Jeong-Sik Nam ,  Sang-Kyun Park ,  Kwang-Hyun Kim ,  Byung-Sik Moon ,  Won-Chang Jung

    发明人： Jeong-Sik Nam ,  Sang-Kyun Park ,  Kwang-Hyun Kim ,  Byung-Sik Moon ,  Won-Chang Jung

    IPC分类号： G11C17/18

    CPC分类号： G11C29/812 ,  G11C29/785 ,  G11C29/787

    摘要： A redundancy program circuit and methods thereof. The redundancy program circuit may include a master fuse circuit with a master fuse outputting an operation enable signal to indicate a master fuse operating status, at least one control fuse circuit including at least one control fuse, the at least one control fuse circuit outputting an operating status signal for the at least one control fuse and a multiplexing unit configured to multiplex decoding address signal bits based on at least one of the operating status signal and the operation enable signal.

    摘要翻译： 一种冗余程序电路及其方法。 冗余程序电路可以包括具有主熔丝的主熔丝电路，其输出用于指示主熔丝运行状态的操作使能信号，至少一个控制熔丝电路，包括至少一个控制熔丝，所述至少一个控制熔丝电路输出操作 用于所述至少一个控制熔丝的状态信号和被配置为基于所述操作状态信号和所述操作使能信号中的至少一个来复用解码地址信号位的复用单元。

    MEMORY DEVICE EMPLOYING OPEN BIT LINE ARCHITECTURE FOR PROVIDING IDENTICAL DATA TOPOLOGY ON REPAIRED MEMORY CELL BLOCK AND METHOD THEREOF
    10.
    发明申请
    MEMORY DEVICE EMPLOYING OPEN BIT LINE ARCHITECTURE FOR PROVIDING IDENTICAL DATA TOPOLOGY ON REPAIRED MEMORY CELL BLOCK AND METHOD THEREOF 失效
    使用开放位线架构的记忆装置，用于在修复的记忆体块上提供标识数据拓扑及其方法

    公开(公告)号：US20060028900A1

    公开(公告)日：2006-02-09

    申请号：US11197227

    申请日：2005-08-04

    申请人： Dong-Hak Shin ,  Ho-Sung Song ,  Byung-Sik Moon

    发明人： Dong-Hak Shin ,  Ho-Sung Song ,  Byung-Sik Moon

    IPC分类号： G11C8/00 ,  G11C7/06 ,  G11C29/00

    CPC分类号： G11C7/18 ,  G11C29/808 ,  G11C29/846

    摘要： A memory device has at least one pair of memory cell blocks, a spare row decoder, a data exchange control signal generator and a data exchange unit. When a defective memory cell in a first memory cell block is repaired with a spare memory cell in a second memory cell block that neighbors (or is adjacent) the first memory cell block, the data topology of the memory cell of the first memory cell may be matched to the memory cell of the second memory cell block.

    摘要翻译： 存储器件具有至少一对存储单元块，备用行解码器，数据交换控制信号发生器和数据交换单元。 当第一存储器单元块中的有缺陷的存储器单元用邻近（或相邻）第一存储器单元块的第二存储器单元块中的备用存储器单元修复时，第一存储器单元的存储单元的数据拓扑可以 与第二存储单元块的存储单元匹配。